JPH0115084B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an on-load tap switching device using a thyristor, and more particularly to an on-load tap switching device that has an improved tap switching system in a specific operating state.

An example of this type of device is the device shown in FIG. In the figure, 1, 2, 3, and 4 are thyristors, 5 is an output winding, and 6 is a tap voltage adjustment winding. 7 is a tap on the high output side, and 8 is a tap on the low output side. Two terminals on the load side of the thyristors connected in antiparallel form a load terminal 9 connected in parallel. A resistor 13 and a capacitor 1 are connected between the other load terminals 0 and 9 of the transformer 10.
A series connection load with 4 is connected. transformer 1
A power supply is connected to primary winding terminals 11 and 12 of 0, and either thyristors 1 and 2 or thyristors 3 and 4 supply electric power to the load by passing current therethrough.

The operation of this device will be explained using the waveform diagrams in FIGS. 2a to 2f. If thyristors 1 and 2 are energized and thyristors 3 and 4 are non-conductive, the load power factor is leading, so the voltage to the load is
V _0-7 and current have a phase relationship as shown in Figure 2a. FIG. 2d shows the numbers of the thyristors in the energized state, and as can be seen from FIG. 2d, the thyristor 1 is in the energized state until time _t2 . At time _t2 , thyristor 1 becomes non-conductive and thyristor 2 becomes energized.

When lowering the tap, the switch is made during the period t ₂ to _{t 4} during which the voltage and current polarities are opposite polarities. When the voltage and current are switched to a period t ₂ to _{t 4} in which the polarities are opposite, no bridging current flows and commutation from thyristor 2 to thyristor 4 becomes possible. FIG. 2 shows a state in which the gate I _G4 (FIG. 2 c) is applied to the thyristor 4 at time t ₃ and commutation is started. The voltage V _8-9 to the non-conducting thyristors 3 and 4 is shown in FIG. 2b, and the currents I ₂ and I ₄ of the thyristors 2 and 4 are shown in FIGS. 2e and f, respectively.

However, when the load power factor approaches 1 due to the leading power factor, the period during which the voltage and current are of opposite polarity becomes short, and the commutation period of the thyristor is not ensured, making commutation impossible.

Generally, there are various means to ensure the commutation period of a thyristor, but this invention temporarily stops the gate signal to the thyristor during commutation, turns off all thyristors, and secures the commutation period of the thyristor. This is an improved on-load tap switching device that ensures the following.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows the on-load tap switching device according to the present invention, particularly its control circuit, in which a current transformer 15 for detecting the load current i is disposed in the same main circuit as shown in FIG. is shown. The current zero point detection circuit 16 inputs the signal from the current transformer 15, the output 17 of the circuit 16 enters the monostable multivibrator (OSM) 18, and the output 19 of the OSM 18
It enters the NOT circuit 20, and its output enters the differentiator 21. Furthermore, the output of the differentiator 21 enters the diode 22, and the output 23 of the diode 22 is
It serves as one input of the AND circuit 25.

The tap lowering command 26 is transmitted to the flip-flop 27
The Q output is input to the set input S of the AND circuit 25. The output 24 of the AND circuit 25 is the set input S of the flip-flop 30, and the Q input of the flip-flop 30 is
The output is an input to a gate amplifier 29, and gate input is applied to the thyristors 3 and 4 by the operation of the gate amplifier 29. flipflop 27
The output of the gate amplifier 31 enters the reset input R of the flip-flop 30, and at the same time becomes the input of the gate amplifier 31. By operating the gate amplifier 31, gate inputs are applied to the thyristors 1 and 2.

Next, the operation will be explained using FIGS. 4a to 4k. In FIG. 4a, the voltage V ₀₇ and the current i applied to the load consisting of the resistor 13 and the capacitor 14 are shown. Initially, thyristor 1 is connected to tap 7 on the high voltage output side as shown in Figure 4i.
Gate inputs are applied to thyristors 1 and 2, and thyristors 1 and 2 are conductive. When the current i is positive, the thyristor 1 is conducting,
When the polarity is negative, the thyristor 2 is in a conductive state.

When the tap-down command 26 is applied to the flip-flop 27 at time _t1 when the current i is in a positive polarity state,
As shown in FIG. 2b, this flip-flop 27
Since the output of thyristors 1 and 2 disappears, the operation of gate amplifier 31 is stopped (FIG. 2h), and therefore the gate inputs of thyristors 1 and 2 are also stopped. As a result, the current i becomes zero at time _t2 (Fig. 4a). Further, as shown in FIG. 4c, the output 17 of the current zero point detection circuit 16 changes to a high level at time t ₂ , and the output 17 causes the OSM 18 to operate for a specified period t ₂ to t _{3 .}
During this period, a high level output 19 is produced (Fig. 4d). The output 19 is inverted by a NOT circuit 20 and then differentiated by a differentiator 21. Among the outputs of the differentiator 21, only the positive output is output as 23 through the diode 22 (FIG. 4e). Since the high level output Q from the flip-flop 27 is input to one of the inputs of the AND circuit 25, the high level output 24 is output at the same time as the output 23 is applied to the other input to the AND circuit 25 (the fourth Figure f). The high level output 24 causes the flip-flop 30 to operate and the Q output 28 to be applied to the gate amplifier 29. As a result, gate input is applied to thyristors 3 and 4,
Load current begins to flow from time _t3 (Fig. 4a).

Since current stops flowing at time _t2 , the thyristor 1, which was energized, has the difference between the voltage V _A appearing at tap 7 of the transformer 10 (Fig. 4a) and the voltage V _C applied to the capacitor 14. The voltage is applied as a reverse voltage. Since the voltage V _A at tap 7 of the transformer 10 changes from positive to negative, it takes a certain specified time t ₂ ~
Once t ₃ has elapsed, a reverse voltage is always applied to thyristor 1 and thyristor 1 is turned off. The reverse voltage V _7-9 to the thyristor 1 is shown in FIG. 4j. The voltage _V8-9 applied to the thyristors 3, 4 operating as a drop tap is shown in FIG. 4k. At time _t3 , a gate input is applied to the thyristor 4, and the thyristor 4 becomes conductive. As a result, the conduction of thyristors 1 and 2 is changed to the conduction of thyristors 3 and 4, and the tap-down operation is completed.

As explained above, the tap-down operation in the advanced operating state where the load power factor is close to 1 is possible by temporarily stopping the load current supply, thereby reliably turning off the thyristor.

Then, by temporarily stopping the load current with the tap-down operation, the full voltage of the transformer output is applied.
If it is inconvenient to increase the withstand voltage of the thyristor or temporarily stop the load current,
As shown in Figure 5 a and b, a non-linear resistor NR is connected in parallel with the thyristor so that the load current flows through NR, and at this time, the voltage appearing on the non-linear resistor NR is made to not exceed the withstand voltage of the thyristor. High reliability can be obtained through coordination.

As described above, according to the present invention, it is possible to perform the tap-lowering operation in an advanced operating state where the load power factor is close to 1 by reliably turning off the thyristor. In addition, when all the thyristors are turned off, since a non-linear resistor is connected between the thyristor terminals at the output of the transformer, if the voltage is above a predetermined voltage, the load current flows through the non-linear resistor, and the terminal voltage is lower than the predetermined value. Therefore, it is possible to protect the thyristor from overvoltage and ensure power supply to the load.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a general thyristor-type tap switching device under load, and Fig. 2 a to f are:
FIG. 1 is a waveform diagram for explaining the operation; FIG. 3 is a block configuration diagram showing the on-load tap switching device according to an embodiment of the present invention, particularly its control circuit;
4a to 4k are waveform diagrams for explaining the operation of FIG. 3, and FIGS. 5a and 5b are tap switching according to an embodiment of the present invention in which a nonlinear resistance is provided in the device shown in FIG. 3. FIG. 2 is a partial circuit diagram of the device. In the figure, 1, 2, 3, 4 are thyristors, 10 is a transformer, 13, 14 are resistors and capacitors indicating loads,
15 is a current transformer for detecting the load current, 16 is a current zero point detector, 18 is a monostable multivibrator, 20 is a NOT circuit, 21 is a differentiator, 22 is a diode (16, 18, 20, 21, 22 ), 25 constitutes a circuit that generates a pulse after a certain period of time.
An AND circuit, 30 a flip-flop, 29 and 31 gate amplifiers. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. An anti-parallel thyristor circuit connected to each of a plurality of taps with different voltages of an AC power adjustment transformer and switching taps in response to the application of a gate signal, and an anti-parallel thyristor circuit connected between the anti-parallel connected thyristor terminals. When lowering the tap in a leading power factor state where the power factor of the load circuit is close to 1 due to the non-linear resistance, a gate amplifier is used that stops the gate signal of the energized first set of thyristors by the tap lowering command. , a circuit that generates a pulse after a certain period of time sufficient to apply a reverse voltage to the first set of thyristors after the load current becomes zero, and a logical product of the tap-down command and the pulse after the certain period of time; 1. A flip-flop circuit which receives a signal obtained by inputting a signal and holds a gate signal to a second set of thyristors on the tap side to be switched.