JPH01155665A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit using a field-effect semiconductor device with an extremely fine structure.

[Conventional technology]

In order to improve the performance of a field effect semiconductor device (hereinafter abbreviated as FET), it is effective to shorten the channel length. However, as the channels become shorter, an undesirable phenomenon called punch-through phenomenon occurs. For example, conventional metal-semiconductor contact gate semiconductor devices (MESFETs)
As shown in FIG. 2, a semiconductor substrate 21, an active layer 22 formed thereon, a source/drain region 23, 23' formed on this active layer 22, and a region formed on the active layer 22 are formed. It consists of a gate electrode 24.

In this MES type semiconductor device, especially in a short channel MESFET aimed at high integration, due to the punch-through phenomenon between the source and drain caused by the applied drain voltage vDI, the drain current in the subthreshold region - gate Voltage characteristics deteriorate. That is, in a short channel MES type semiconductor device, an undesirable characteristic occurs that a punch-through current flows between the source and drain and the drain current is not completely pinched off, compared to a long channel MES type semiconductor device.

This phenomenon is observed not only in MESFETs but also in metal-oxide semiconductor devices (MOSFETs), junction gate semiconductor devices (JFETs), and the like.

[The problem that the invention attempts to solve]

As a means of solving this phenomenon, a method has previously been proposed in which a layer locally doped with impurities is provided below the channel layer to prevent punch-through (for example, Japanese Patent Laid-Open No. 116875/1982). .

On the other hand, in recent years, δ-FET has been proposed as a method to increase the current drive capability of MESFET (for example, E.F. Schubert, I.E.E.E.D.
-Volume 33, No. 5.

Page 625 (1986) (E, F, S
Chubertejal IEEE' Vol.
ED-33, No. 5゜pp, 625 (1986))
), which differs from conventional MESFETs and MOSFETs by creating a layer doped with impurities according to the δ function in the crystal.
This is used as a channel. This δ−F
Although ET is certainly improved in terms of driving capability, it is still difficult to eliminate punch-through when the channel is shortened.

Therefore, by combining the two, it is possible to realize a FET that has high driving capability and is resistant to punch-through.

However, in this δ-FET, E-type FET and D-type FE
It is difficult to fabricate an integrated circuit by manufacturing T and T on the same substrate.

[Means to resolve the issue]

In the present invention, the above-mentioned drawbacks are solved and E-type and D-type are placed on the same substrate.
It provides a means for making FETs of the same type and realizing integrated circuits.

The reason why a punch-through current flows in a short channel MES type semiconductor device is that the drain depletion layer extends toward the source side, and the drain depletion layer and the source depletion layer directly influence each other.

In the present invention, two important concepts are clarified in order to suppress punch-through. First, it is important to suppress the spatial spread of current distribution and realize a one-dimensional current distribution. The second is to prevent the bulge of the equipotential lines from extending toward the source side. That is, it is a spatial and electrical shielding effect of the drain electric field.

In order to realize the above two important concepts, at least two special impurity layers are required to be provided on the semiconductor substrate. That is, the first layer is located at a position close to the surface, and the second layer is located at a position where the potential expansion is greatest. The first layer must be formed with an impurity of the same conductivity type as the source (or drain) impurity in order to function as an active layer, and the second layer must be formed with an impurity of the opposite conductivity as the first layer in order to function as a punch-through stopper. Must be. Moreover, in order to effectively realize the above two concepts, it is necessary to form a layer with a high impurity concentration and a dimensionally thin layer.

Next, in order to realize an integrated circuit, it is necessary to use a D-type FET whose channel is in the ON state when no voltage is applied to the gate.
It is necessary to simultaneously create an E-type FET that is in the OFF state. If we try to realize this using only MESFETs, we will need two types of MESFETs with different distances from the channel layer to the gate electrode.
I have to make an SFET. To do this, it is common practice to first form an epitaxial layer with a large distance between the channel layer and the gate electrode to create a D-type FET, and then partially etch it to shorten this distance to create an E-type FET. This is a typical method. However, with this method, the D-type FE
Although T can be easily formed, it has the disadvantage that it is very difficult to control when manufacturing an E-type FET.

Therefore, by fabricating a MOSFET on the same substrate as the D-type FET, an E-type FET can be realized.

[Operation] By introducing the two important concepts described above, carriers flow through an extremely thin active layer, resulting in a nearly one-dimensional spread distribution, and furthermore, a phenomenon in which the equipotential lines extend toward the source side is also observed. This makes it possible to obtain good electrical characteristics.

It goes without saying that the electrical effect of such a special impurity layer can be applied not only to MES type semiconductor devices but also to MOS type semiconductor devices, even in cases where the substrate has a heterojunction - inside the shell.

Next, regarding integration into circuits, the surface electric field of the MOSFET can be made larger than that of the MESFET, so M
An E-type FET can be realized in the OSFET part, and the D-type FE described above can be realized.
Since both types of FETs are formed in combination with T, an integrated circuit can be realized.6 [Embodiments] The present invention will be described in detail below with reference to embodiments.

Example 1 As shown in FIG. 1(a), for a low impurity concentration n-type (100) silicon substrate 11 with a resistivity of 20 Ω·cm,
Using molecular beam epitaxial method, boron has an areal density of 4
A very thin p+ type S+ layer 12 doped with IO 11 cm-2 is formed, followed by 3 P- type Sit layers 12.
A thickness of 00 nm is deposited. Here, arsenic is doped at a surface density of 4×10'2 CI11-2 to form an n-type high concentration ultra-thin layer 13. Furthermore, 30n of P-type silicon 11'
A substrate having two layers of n'' JP+ type is formed from one surface by depositing m.

Next, the substrate temperature is raised to 750°C and oxygen is introduced to form a thin oxide film 14 on the surface (Fig. 1(b)).
. This oxide film becomes the gate oxide film for MOSFET, but it is too thin as it is, so it is made by CVD method etc.
Two additional films are deposited to a total thickness of 20 nm.

After that, the 5i02 film is removed by dry etching only in the area to be used as MESFET (Fig. 1(c)).
, and then as the gate electrode 15.

AQ was formed by vapor deposition.

Of course, an electrode material such as polysilicon, silicide, W, etc. may be deposited. Note that the source/drain electrode portions were formed by p+ ion implantation. Formation conditions are 150KeV
, 5×10”cm=, annealing at 650° C. for 8 hours.

Through the above steps, MOSFET17 becomes an E-type FET, and MESFET1 becomes a D-type FET.
6 can be fabricated on an St substrate (Fig. 1(d)
).

In this example, only Si was described, but a good quality MOSF
It goes without saying that if ET can be realized, it can also be applied to other semiconductor materials such as GaAs.

Now, the characteristics of the FET manufactured here are shown as a solid line 31 in FIG.

The gate length of this MESFET was 1 μm.

For comparison, a semiconductor device with a structure without the second layer 12 from the surface was also manufactured, and its current-voltage characteristics are shown by the broken line 3 in FIG.
Shown as 2. In this way, in a short channel MESFET, a structure having both n-type and n-type impurity layers at the same time is
Compared to a structure with only one mold layer, punch-through is suppressed and it is possible to obtain good electrical characteristics.

On the other hand, in the MOS FET, no current flows when the gate voltage is O because of the surface electric field, proving that it is an E-type FET.

〔Effect of the invention〕

As explained above, according to the present invention, the gate length is 1 μm.
Good electrical characteristics can be achieved down to the submicron region without punch-through. By making such semiconductor devices into MES type and MOS type,
n A, it is possible to realize an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the manufacturing process of a semiconductor integrated circuit in an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the structure of a conventional MESFET, and FIG. 3 is a characteristic of the semiconductor integrated circuit in an embodiment of the present invention. FIG. 5. Explanation of symbols 11...Silicon substrate, 12...P+ silicon layer. 11', 11'... P-silicon layer, 13... n-type high concentration layer, 14... oxide film, 15... gate electrode. 16...MESFET, 17...MOSFET. 21... Semiconductor substrate, 22... Active layer, 22.23
'...Source/drain region, 24...Gate, G electrode.

Claims (1)

[Claims] 1. A semiconductor integrated circuit having both an MES type field effect semiconductor device and a MOS type field effect semiconductor device, wherein each of the two types of semiconductor devices has a thickness of 5 to 200 Å higher than the impurity concentration of the base semiconductor. 1. A semiconductor integrated circuit comprising at least two impurity layers, one of the two impurity layers having the same conductivity type as a base impurity, and the other having a conductivity type opposite to the base impurity.