JPH0328066B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a field effect transistor using a semiconductor heterojunction that is applied to low-noise amplifier circuits, high-speed integrated circuits, and optical high-density integrated circuits.

(Prior art) Conventionally, on an indium-phosphorus substrate 21 as shown in FIG. has a wide forbidden band layer 25 made of an aluminum-indium-arsenic mixed crystal semiconductor layer 24 doped with A field effect transistor characterized by having a source electrode 27 and a drain electrode 28 has been proposed and prototyped (CYChen et al., Electron Device Letters ((IEEE Electron
Device Letters) EDL-Volume 3, No. 6 (1982),
152 pages). In the field effect transistor, a two-dimensional electronic layer 29 is formed along a wide bandgap layer 25 in a gallium-indium-arsenic mixed crystal semiconductor layer 22, and this two-dimensional electronic layer 29 forms a channel to form a source electrode 27. A current path is formed between the drain electrode 28 and the drain electrode 28 . The transistor operation of the field effect transistor is realized by modulating the secondary electron density under the gate electrode region by the voltage applied to the gate electrode 26. In this field-effect transistor, the gallium-indium-arsenic mixed crystal semiconductor has a high electron mobility exceeding 10,000 cm ² /V sec at room temperature, so the mutual conductance, which represents device performance, is about
High values of 440mS/mm and approximately 700mS/mm at 77K have been achieved (12th International
Symposium on Gallium Arsenide and
Related Compounds Abstract, 5 pages, lecture number Opening Session 2, Karuizawa 1985).

(Problems to be Solved by the Invention) In the field effect transistor according to the prior art, the source resistance has a value that cannot be ignored, so transistor characteristics such as mutual conductance and noise figure are limited by the source resistance. Therefore, in order to improve the characteristics of the field effect transistor, it is necessary to further reduce the source resistance than in the prior art.

In order to reduce the source resistance using conventional technology, n-type impurities are implanted between the source electrode and the gate electrode and between the gate electrode and the drain electrode using ion implantation, and by flash annealing, etc. One possible method is to activate the impurities and reduce the resistivity of these regions. but,
According to experiments conducted by the present inventors, in a field effect transistor equipped with a wide bandgap layer consisting only of the aluminum-indium-arsenic mixed crystal semiconductor layer, n-type impurities ion-implanted into the aluminum-indium-arsenic mixed crystal semiconductor layer The activation rate is low, and the electron mobility in the aluminum-indium-arsenic mixed crystal semiconductor is 300 cm ² /V.
It is difficult to sufficiently reduce the resistivity of the implanted aluminum-indium-arsenic mixed crystal semiconductor layer due to the low resistivity of less than 1.5 seconds, and as a result, even if ion implantation technology is used in the conventional field effect transistor, It was found that it was not possible to sufficiently reduce the source resistance and that it was difficult to improve the characteristics.

(Means for Solving the Problems) In order to solve the above-mentioned problems, in the present invention, the wide bandgap layer is composed of an aluminum-indium-arsenic mixed crystal semiconductor layer and an indium-phosphorus layer, and at least the source electrode and the gate In this method, an n-type impurity is ion-implanted between the electrodes and between the gate electrode and the drain electrode.

(Function) Experimental results of ion implantation and annealing of n-type impurities into indium and phosphorus (Applied Physics Letters)
43, No. 15 (1983, p. 381)), with indium-phosphorus, an activation rate of 60% or more can be obtained, and an electron mobility of 2000 cm ² /V·sec or more can be obtained in the injection layer. As a result, when 10 ¹⁴ cm ^-2 of n-type impurities are implanted, the sheet resistance of the implanted layer can be reduced to 50 Ω/hole or less for indium and phosphorus. On the other hand, when the present inventor conducted an experiment on an aluminum-indium-arsenic mixed crystal semiconductor, the sheet resistance reached a value of about 1KΩ/socket. This is due to the high electron mobility and activation rate in indium phosphorus.

From the above results, it was found that in a field effect transistor characterized by having a wide band gap layer on a gallium-indium-arsenic mixed crystal semiconductor layer and performing ion implantation between electrodes for the purpose of reducing source resistance. It is understood that it is effective to use an indium-phosphorus layer as a wide bandgap layer.

However, using only the indium-phosphorus layer as the wide bandgap layer creates new problems as follows. That is, in the field effect transistor, the gate electrode needs to be formed so as to form a shot junction with the wide bandgap layer;
It is generally difficult to form a Schottky junction with indium-phosphorus.

Therefore, in the present invention, by newly forming a multilayer aluminum-indium-arsenic mixed crystal semiconductor layer and an indium-phosphorus layer that can easily form a Schottky junction as a wide bandgap layer, good gate characteristics and ion implantation can be achieved. At the same time, an effective reduction in source resistance was achieved. That is, the wide band gap layer has a multilayer structure of two or more layers consisting of an aluminum/indium/arsenic mixed crystal semiconductor layer and an indium/phosphorus layer, and at least the layer closest to the gate electrode is an aluminum/indium/arsenic mixed crystal semiconductor layer. This makes it possible to achieve good gate characteristics, and since the wide bandgap layer includes an indium/phosphorus layer that can easily reduce resistance by ion implantation, the source resistance can be effectively reduced by ion implantation. can be realized simultaneously. As a result, the present invention has achieved high mutual conductance and a low noise figure by making full use of the feature of having two-dimensional electron channels formed in a gallium-indium-arsenic mixed crystal semiconductor with high electron mobility. It becomes possible to realize a field effect transistor having the following characteristics.

(Example) An example of the present invention is shown in FIGS. 1a, b, and c. In the embodiment shown in FIG. 1a, a buffer layer 2 made of an aluminum-indium-arsenic mixed crystal semiconductor is formed on an indium-phosphorous substrate 1 by metal organic chemical vapor deposition (MOCVD) or gas source molecular beam epitaxial growth. Then, a gallium-indium-arsenic mixed crystal semiconductor layer 3, an indium-phosphorus layer 4, and an aluminum-indium-arsenic mixed crystal semiconductor layer 5 are formed. Here, the buffer layer 2 is provided to improve the crystallinity of the epitaxially grown layer and to prevent diffusion of impurities from the substrate 1, and may not be provided depending on required characteristics. The thickness of each layer varies depending on the design value of the threshold voltage, etc., but typical values are approximately 0.5 μm for the buffer layer 2 and 20 nm for the gallium-indium-arsenic mixed crystal semiconductor layer 3.
from 200nm, indium/phosphorus layer 4 from 10nm
The thickness of the aluminum-indium-arsenic mixed crystal semiconductor layer 5 is about 10 nm. The impurity addition to each layer varies depending on design values such as threshold voltage, but typical examples include threshold voltage uniformity and
If reproducibility is important, all layers should be additive-free.
When taking out a large current is important, an n-type impurity of about 2×10 ¹⁸ cm ⁻³ is added to the indium-phosphorus layer 4. In the latter case, the gallium/indium/arsenic mixed crystal semiconductor layer 3 of the indium/phosphorous layer 4
In order to prevent roughness of the heterojunction surface due to diffusion of n-type impurities, no impurity may be added to the region approximately 10 nm from the side.

After epitaxial growth as described above is performed, the low resistance region 6 is formed by ion-implanting n-type impurities such as silicon or selenium and annealing. Furthermore, ohmic electrodes made of gold, germanium, etc. are deposited and alloyed to form the source electrode 7 and the drain electrode 8. Furthermore, a gate electrode 9 made of aluminum, platinum, tungsten silicide, or the like is formed. here,
It is desirable that the low resistance region 6 into which n-type impurities are ion-implanted not overlap the gate electrode 9 in order to reduce parasitic capacitance and improve reverse breakdown voltage.
FIG. 1b shows an embodiment that can reliably eliminate this overlap. If the alignment accuracy of photolithography technology is insufficient and the reproducibility of device characteristics is not good, it is important to use self-alignment technology using heat-resistant gates or dummy gates. It will be different from. However, regardless of whether or not self-alignment technology is used, the present invention makes it possible to effectively reduce the source resistance, thereby realizing a field effect transistor with high mutual conductance and low noise.

In the embodiment shown in FIG. 1c, the channel 2
In order to enhance the quantum mechanical confinement effect of dimensional electrons, an aluminum/indium/arsenic mixed crystal semiconductor layer 10 is further provided between the gallium/indium/arsenic mixed crystal semiconductor layer 3 and the indium/phosphorus layer 4. be. Since the electron affinity of the mixed crystal semiconductor layer 10 is smaller than that of the indium-phosphorous layer 4, a high energy barrier is formed against two-dimensional electrons in the gallium-indium-arsenic mixed crystal semiconductor layer 3. As a result, the effect of quantum mechanical confinement of two-dimensional electrons is enhanced, and good transistor characteristics can be obtained even when a high gate voltage is applied.

(Effects of the Invention) The present invention makes it possible to realize a field effect transistor with high mutual conductance and a low noise figure, making a great contribution to application fields such as low-noise amplifier circuits, high-speed integrated circuits, and optical integrated circuits. It is something that does.

[Brief explanation of the drawing]

FIGS. 1a, 1b and 1c are cross-sectional views of a field effect transistor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a conventional field effect transistor. 1, 21: indium/phosphorous substrate, 2: buffer layer, 3, 22: gallium/indium/arsenic mixed crystal semiconductor layer, 4: indium/phosphorous layer, 5, 10:
Aluminum-indium-arsenic mixed crystal semiconductor layer,
6: Low resistance region implanted with n-type impurities, 7, 2
7: source electrode, 8, 28: drain electrode, 9,
26: Gate electrode, 11, 25: Wide bandgap layer,
23: Aluminum-indium-arsenic mixed crystal semiconductor layer with no impurities added, 24: Aluminum-indium-arsenic mixed crystal semiconductor layer added with n-type impurities, 29: Two-dimensional electronic layer.

Claims (1)

[Claims] 1. Located on an indium-phosphorous substrate, having a gallium-indium-arsenic mixed crystal semiconductor layer, and an indium-phosphorus layer and an aluminum-indium-arsenic mixed crystal semiconductor layer on the mixed crystal semiconductor layer. a wide bandgap layer consisting of at least two layers; a gate electrode on the aluminum-indium-arsenic mixed crystal semiconductor layer; a source electrode and a drain electrode facing each other on both sides of the gate electrode; n in the region containing the indium/phosphorus layer between the gate electrode and between the gate electrode and the drain electrode.
A field effect transistor characterized by ion implantation of type impurities. 2. The field effect transistor according to claim 1, wherein part or all of the wide bandgap layer is n-type before ion implantation. 3. The field effect transistor according to claim 1, wherein part or all of the wide bandgap layer is not doped with impurities before ion implantation. 4. The field effect transistor according to claim 1, further comprising an aluminum/indium/arsenic mixed crystal semiconductor layer formed on the indium/phosphorous substrate side of the gallium/indium/arsenic mixed crystal semiconductor layer.