JPH01160537A - Ultrasonic diagnostic apparatus - Google Patents

Abstract

PURPOSE:To magnify the dynamic range of a signal to be handled, by constituting an A/D converter circuit of a multiplier making the dynamic range of an analogue echo signal variable, an A/D converter and a data converter for converting the output data of the A/D converter. CONSTITUTION:The analogue signal from a delay circuit 13 of an analogue system is inputted to the first A/D converter 23a as it is and inputted to the second converter 23b while the dynamic range of the signal is made variable by a multiplier 22. When k=5 is set in the multiplier 22 and the magnification thereof is set to 1/2<5> while m=10 is set in the first and second A/D converters 23a, 23b and the number of bits thereof are set to 10bits, two 10-bit A/D converters (23a, 23b) are used from the relation between the input and output data from the first and second A/D converters 23a, 23b to a data converter 24 to realize an A/D converter circuit 14 having a 15-bit dynamic range as a whole.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an ultrasonic diagnostic apparatus that uses ultrasonic waves to obtain a tomographic image of a diagnostic region of a subject, and particularly relates to an A/D converter with a small number of bits. The present invention relates to an ultrasonic diagnostic apparatus having a digital phasing circuit equipped with an A/D conversion circuit that can expand the dynamic range of signals handled even when used.

[Conventional technology]

Conventional ultrasonic diagnostic equipment equipped with a phasing circuit using a delay line has a large delay time error, and there are variations in the sending direction of the ultrasound beam and the receiving direction of reflected echoes, making it difficult to obtain high-quality tomographic images. It was difficult to obtain. On the other hand, in the past, IEE, Ultrasonic Symposium Proceedings 2 (1980
) pages 22 to 31 (IEEE, UltAoni
c SymposiumProceedings2 (
1980) P, 22-31), an ultrasonic diagnostic apparatus equipped with a digital phasing circuit has been proposed.

As shown in FIG.
, . . 1n arranged in a line and transmitting and receiving ultrasonic waves, and a pulse generator that applies a drive pulse for emitting ultrasonic waves by giving a predetermined delay time to each of the transducer elements 1a to 1n. 3 and each transducer element 1a to 1n of the probe 2
An A/D converter 4 that converts the analog echo signal received by the
A plurality of RAMs (random write/read memories) 5a, 5 serve as storage devices that sequentially store digital signals from the
b, . . 5n, an adder 6 that adds the data read out from these RAMs 5a to 5n, and a display device 7 that converts the output signal from the adder 6 into a D/A and displays a tomographic image. consists of

In addition, in FIG. 8, reference numeral 8 is a changeover switch, and reference numeral 9 is a changeover switch.
10 is an amplifier, 10 is a D/A converter, 11 is a focus memory, and 12 is a control section. Then, the probe 2 transmits an ultrasonic beam, and the echo signals received by the transducer elements 1a to 1n are converted into digital signals by the A/D converter 4, which are stored in the RAMs 5a to 5n.
The controller 12 and focus memory 11 control the data address and read timing to give a predetermined delay, and the read data is stored in the adder 6.
The phasing is performed by adding . That is, the A/D converter 4, the RAMs 5a to 5n, and the adder 6 constitute a digital phasing circuit.

In addition, in FIG. 8, the echo signals from each transducer element 1a to 1n of the probe 2 are sequentially switched using a changeover switch 8 such as a multiplexer, and the number of A/D converters 4 is one. However, the above-mentioned document describes that a plurality of A/D converters 4 that operate in parallel may be provided in order to perform high-speed imaging in real time.

[Problem that the invention seeks to solve]

In an ultrasonic diagnostic apparatus equipped with such a digital phasing circuit, each transducer element 1a, lb of the probe 2
,...one A/D for each 1n channel
Converter 4 is connected. here,
The dynamic range of the echo signal was determined by the number of bits of the A/D converter 4. Therefore, if you want to widen the dynamic range of the echo signal handled, it is necessary to use an A/D converter 4 with a large number of bits.
was necessary. Further, A/D converters with a large number of bits are expensive, which poses an obstacle to putting the device into practical use.

Furthermore, in recent ultrasound diagnostic equipment, the a
Along with this, so-called pulsed Doppler blood flow measurement, which measures blood flow velocity by measuring the Doppler shift frequency of reflected echoes of blood cells in the heart and blood vessels, has begun to be performed. When trying to apply the echo signals to a human body, the echo signals from blood cells in the blood are much weaker than the echo signals forming a tomographic image, so the dynamic range of the echo signals handled as a whole becomes even wider. Incidentally, the dynamic range of the echo signal that forms the tomographic image is a large value of 40 to 60 dB, and if we try to give it the function of pulse Doppler blood flow measurement,
The dynamic range of the echo signal handled is approximately 9C)d
It is wide up to B. On the other hand, since the ultrasonic waves used in ultrasonic diagnostic equipment have a high frequency of 2.0 MHz to 10 MHz, the A/
The D converter 4 has 10 bits or more (more preferably 1
5 bits or more) and the sampling rate is 4 to 30 MHz.
A high-speed device is required. Such high speed A/D
It is not easy to secure the large number of bits necessary for the converter 4, and even if it could be secured, it would be very expensive. Therefore, it has been difficult to put into practical use an ultrasonic diagnostic apparatus equipped with a digital phasing circuit.

Therefore, the present invention provides an ultrasonic diagnostic apparatus having a digital phasing circuit equipped with an A/D conversion circuit that can expand the dynamic range of signals handled even when using an A/D converter with a small number of bits. The purpose is to provide

[Means for solving problems]

Means of the present invention for solving the above problems includes a probe in which a plurality of transducer elements are arranged in a line and transmits and receives ultrasonic waves;
A pulse generator that applies a perturbation pulse of ultrasonic wave emission to each transducer element with a predetermined delay time, and converts the analog echo signal received by each transducer element of the probe into a digital signal. an A/D conversion circuit; a storage device that sequentially stores digital signals from the A/D conversion circuit; an adder that adds data read from the storage device with a predetermined delay; The output signal of D
In the ultrasonic diagnostic apparatus, the A/D conversion circuit includes a multiplier that varies the dynamic range of the analog echo signal, and a display device that displays a tomographic image by performing A/A conversion. An ultrasonic diagnostic apparatus consisting of an A/D converter that converts an analog echo signal into a digital signal, and a data converter that converts the output data of the A/D converter in accordance with the magnification of the multiplier. It will be done.

[For production]

The ultrasonic diagnostic apparatus configured in this way varies the dynamic range of the analog echo signal with a multiplier in the A/D conversion circuit, and converts the analog echo signal from the multiplier into a digital signal with the A/D converter. Then, the data converter converts the above A according to the magnitude of the magnification of the multiplier.
By converting the output data of the /b converter, for analog echo signals from each channel of the probe,
It can be converted into a digital signal by an A/D converter whose conversion coefficient changes depending on the signal size, and the A/D converter described above can be converted into a digital signal.
The output data of the D converter can be shifted by a predetermined number of digits and output.

The operation of the A/D converter will now be explained in more detail, assuming that the A/D converter uses two 10-bit, ie, 10 binary digit, A/D converters. The relationship between the magnitude of the readable input signal and the magnitude of the output signal in that case is shown in FIG. Note that the horizontal and vertical axes in FIG. 2 are expressed in decimal numbers and dB, respectively. Second
In the figure, straight line A represents the first A/D converter, and when a signal with a size from 1 to 1024 in decimal notation is input, the first A/D converter It outputs a binary digital signal corresponding to 1 to 1024 in decimal.

On the other hand, the magnification of the multiplier of the A/D conversion circuit is set to 1/32, for example.
, that is, approximately -30 dB, the second A/D converter shown by line B will have a decimal value of 32 to 327.
When a signal with a size up to 68 is input, a binary digital signal corresponding to the decimal numbers 1 to 1024 is output in response to the input signal. From the relationship between straight line A and straight line B shown in FIG.
Point b on the output signal of the second A/D converter (straight line B) at point a1 where the output signal of A) is 1024 in decimal
By switching to □ and then reading along straight line B, the input signal as a whole is 1 to 32768 in decimal.
Changes over this range can be read and output as a digital signal. That is, the second
In the example shown in the figure, the total is approximately 90 dB (15
It is possible to convert an analog signal into a digital signal with a dynamic range of Here, since the magnification of the multiplier is 1/32 = 1/25, the A/D
If the converter outputs binary numbers in parallel, shifting to the upper 5-bit digit will output a binary digital signal corresponding to the input signal.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of an ultrasonic diagnostic apparatus according to the present invention.

This ultrasonic diagnostic device uses ultrasonic waves to obtain tomographic images of the diagnostic area of a subject, and uses a digital delay circuit that utilizes the characteristics of analog delay circuits and can compensate for their shortcomings. As shown in FIG. 1, the probe 2, the pulse generator 3, the analog delay circuit 13, and the A/D conversion circuit 14
, a storage device (5a, 5b, -5n), and an adder 6.

and a display device 7.

The probe 2 transmits and receives ultrasonic waves toward the diagnostic site of the subject, and has a plurality of transducer elements 1a, lb, . . . 1n formed in small strip shapes arranged in a line. ing. The pulse generator 3 is connected to each transducer element 1 of the probe 2.
A driving pulse for ultrasonic wave launch is applied by giving a predetermined delay time to a to 1n, and a control unit 12 (to be described later) controls each transducer element 1a to control the transmission direction of the ultrasonic beam.

It is possible to control the timing of exciting 1b, . . . 1n.

The analog delay circuit 13 provides a predetermined delay time to the echo signals received by the transducer elements 1a, lb, . . . 1n of the probe 2 from the diagnostic site of the subject. , an amplifier 15, a delay circuit 16, a voltage/current converter 17, a cross point switch 18, a constant current signal source 19, and a tapped delay line 20. The amplifier 15 includes each transducer element 1a, lb, . . . of the probe 2.
This is for amplifying the echo signal from the 1n, and the gain is increased over time according to the control signal from the control unit 12 to compensate for the echo signal becoming weaker in the deep part of the subject. The delay circuit 16 consists of a tapped delay line and an analog switch, and is designed to delay the echo signal from the amplifier 15 with a small delay time. For example, if the delay time between each tap of the tapped delay line is T□, and the number of taps is N□, then T
The delay time can be set with a resolution of 1, and the maximum delay time is (
N1-1) T□. The voltage/current converter 17 converts the echo signal voltage from the delay circuit 16 into a constant current signal source. The cross point switch 18 is n
□ The input signal line of the channel and the output signal line of the m channel are made to intersect as shown in the figure, and analog switches are provided at each intersection point, and the opening and closing of these analog switches is controlled by the control unit 12. It's about to be controlled. The constant current signal source 19 has a low input impedance, and is connected to the tap of the subsequent tapped delay line 20 with a signal source as high as possible in impedance to prevent deterioration of the performance of the delay line and to avoid cross points. This prevents insertion loss of the switch 18 and deterioration of frequency characteristics.

Additionally, it also has the effect of adding the signals connected and guided to the constant current signal source 19.

The tapped delay line 20 provides a larger delay than the delay circuit 16, and for example, the delay time between each tap is T.
2 and the number of taps is N2, the delay time can be set with a resolution of T2, and the maximum delay time is (Nz 1)
It becomes Tz. Here, the delay time T2 between each tap is set smaller than the maximum delay time (N1-1)T□ of the delay circuit 16.

The A/D conversion circuit 14 is the analog delay circuit 1
This converts the analog signal output from 3 into a digital signal. The storage device is the A/D conversion circuit 14
It sequentially stores digital signals output from
For example, it consists of a plurality of RAMs 5a, 5b, . . . 5n. The data stored in the RAMs 5a to 5n is read out at an arbitrary cycle of the clock signal output from the control section 12, thereby being delayed by a predetermined delay time. For example, if the cycle of the clock signal for reading the RAMs 5a to 5n is T, and an arbitrary natural number is N, then each RAM 5a is read after N, T hours.

By reading the data of 5b,...5n, N,
A 13 hour delay can be provided. Furthermore, this RA
The delay due to read control of M 5 a to 5n is as follows.

This provides a delay greater than that of the tapped delay line 20 described above. The adder 6 adds the data read from the RAMs 5a to 5n, thereby phasing the data. Then, the A/D conversion circuit 14 and the RAM 5
A to 5n and the adder 6 constitute a digital phasing circuit.

The display device 7 displays a tomographic image by D/A converting the signal output from the adder 6 detected by the detector 21, and has a D/A converter therein.

In FIG. 1, reference numeral 12 is a control section that controls each of the above-mentioned components. Further, although FIG. 1 shows an example in which an analog type delay circuit 13 is provided between the probe 2 and the A/D conversion circuit 14, the present invention is not limited to this. Without providing the delay circuit 13,
All delays may be applied when reading from RAMs 5a to 5n.

In the present invention, the A/D conversion circuit 14 includes a multiplier 22, two A/D converters 23a and 23b, and a data converter 24, as shown in FIG. ing. The multiplier 22 is used to vary the dynamic range of the analog signal output from the analog delay circuit 13 shown in FIG.
/2' (k is an integer), and functions as an attenuator. This multiplier 22 is used to make the levels of input signals to two A/D converters 23a and 23b, which will be described later, different. Note that the multiplier 22 is not limited to an attenuator, but may be an amplifier with a constant gain. The A/D converters 23a and 23b convert an analog signal whose dynamic range has been varied by the presence of the multiplier 22 into a binary digital signal, and both are of m bits.
A first A/D converter 23a and a second A/D converter 23b are provided in parallel, and the multiplier 22 is inserted before the second A/D converter 23b.

The data converter 24 converts the output data of the two A/D converters 23a and 23b in accordance with the magnitude of the magnification of the multiplier 22. In addition, in Figure 3,
Reference numeral 25 inputs the output data from the first A/D converter 23a, compares it with a built-in reference value (a value equal to the number of bits of the first A/D converter 23a), and sends it to the data converter 24. The first A/D converter 23a and the second A/D converter 23a
This is a comparator that sends out a switching signal for the /D converter 23b.

Next, the operation of the A/D conversion circuit 14 configured as described above will be explained. First, analog delay circuit 13
The analog and digital signals from the first A/D converter 23
Input it as is to a, and input it to the second A/D converter 23b.
The dynamic range of the signal is varied by a multiplier 22 and then input. As a result, the levels of the input signals to the first and second A/D converters 23a and 23b are made different. That is, the second A/D converter 23b
In this case, the analog signal is attenuated to 1/2 by the multiplier 22 and inputted. Next, such an analog input signal is sent to the first A/D converter 23a and the second A/D converter 23a.
The converter 23b converts them into binary digital signals and outputs them. Here, the analog input signal to the first A/D converter 23a is small, and the analog input signal to the first A/D converter 23a is small.
If the number of digits of the output data from the A/D converter 23a is small, the comparator 25 compares it with its built-in reference value,
The data converter 24 is controlled to take in output data from the first A/D converter 23a. Therefore, until the number of digits of the output data from the first A/D converter 23a overflows, the second A/D converter 23a
3a is sent to the RAM 5 via the data converter 24.
It is output to a to 5n. Above, we have described the operation of comparing the signal of the first A/D converter 23a with the reference value built into the comparator 25, but we can also consider a modification in which the same operation is performed using the signal of the second A/D converter 23b. It will be done.

Next, the analog input signal to the first A/D converter 23a increases successively, and the analog input signal to the first A/D converter 23a increases.
When the number of digits of the output data from the first A/D converter 23a overflows, the comparator 25 compares it with its built-in reference value and detects that the number of digits of the output data of the first A/D converter 23a has overflowed. , sends a switching signal to the data converter 24 to switch from the first A/D converter 23a to the second A/D converter 23b. Thereby, the data converter 24 takes in the output data from the second A/D converter 23b, and outputs the output data from the second A/D converter 23b to the RAMs 5a to 5n. At this time, the analog signal is attenuated to 1/2 by the multiplier 22 and is input to the second A/D converter 23b.
The output digital signal from 3b is sent to the data converter 2
4 is shifted by bits (k digits) to higher digits and output. Therefore, the total output data from the data converter 24 is a (k 10m )-bit digital signal.

Here, in the multiplier 22 shown in Fig. 3, m = 5 and the magnification is 1/25, and in the first and second A/D converters 23a and 23b, m = 10 and the number of bits is 10 bits. The relationship between the input data and output data from the first and second A/D converters 23a and 23b to the data converter 24 at this time is shown in FIG.

In other words, two 10-bit A/D converters (23
a, 23b), an A/D conversion circuit 14 having an overall dynamic range of 15 bits is realized. This relationship is exactly the same as the relationship shown in FIG. 2 described above. Note that the data converter 24 having the above-mentioned functions can be easily realized by, for example, a combination of gate circuits or a combination of a gate circuit and a shift register.

In addition, in Fig. 3, two A/D converters (2
3a, 23b) Although an example is shown in which they are provided in parallel, the present invention is not limited to this, and three or more may be provided in parallel.For example,
Part 2 regarding the case where three A/D converters are installed in parallel.
If a graph similar to the one shown in the figure is drawn, it will be as shown in FIG. In the figure, straight line A represents the first A/D converter, straight line B represents the second A/D converter, and straight line C represents the third A/D converter.

Here, in FIG. 2, the vertical axis shows the output signal level of the A/D converter, which is
It is equal to the S/N due to converter quantization noise. Therefore, from the first A/D converter (line A) to the second A/D converter
When switching to a converter (straight line B), as shown in Figure 2, when the operating point moves from point a1 on straight line A to point b1 on straight line B, the S/N drops once and then rises again. I will do it. On the other hand, if a third Δ/D converter connected to a multiplier with a magnification smaller than 1732 is further added, as shown by straight line C in FIG. to the third A/D converter (straight line C), and then from the third A/D converter (straight line C) to the second A/D converter (straight line B)
When switching to , the operating point moves from point a on straight line A to point C on straight line C, and then the operating point moves from point c2 on straight line C to point b on straight line B. Become.

At this time, since the above points C□ and S are maintained at a relatively high output signal level, S/
It is possible to suppress the decrease in N and improve the S/N as a whole. From this, as the number of A/D converters installed in parallel increases, the temporary S/D
The decrease in H can be improved. However, increasing the number of A/D converters increases the cost, so it is better to consider the balance between the performance obtained and the cost when putting it into practical use.

FIG. 6 is a block diagram showing a second embodiment of the A/D conversion circuit 14. The A/D conversion circuit 14 according to this embodiment includes a sample hold circuit 26, two voltage dividers 27a,
2'7b, two A/D converters 2ka and 2kb, and a data converter 29. The sample and hold circuit 26 inputs and samples the analog signal output from the analog delay circuit 13 shown in FIG. 1, and holds the value for a certain period of time.

The voltage dividers 27a and 27b function as the multiplier 22 shown in FIG. The pressure gauge 27a has a partial pressure ratio (
1/2', where j is a constant integer) is fixed, and the second voltage divider 27b has a dividing pressure ratio (1/2', where k is an integer).
is said to be variable. Regarding the voltage division ratio of 1/23 of the second voltage divider 27b, the integer is determined by the controller 30, which will be described later.
It is designed to be changed by a control signal from.

Therefore, the two voltage dividers 27a.

27b, two A/D converters 2ka, which will be described later,
The levels of the input signals to the 2kb can be different. A/D converter 2ka.

2 kb converts the analog signal whose dynamic range has been varied by the voltage dividers 27a and 27b into a binary digital signal, and the first A/D converter 2
ka is assumed to be of m bits, and the second A/D converter 2kb is assumed to be of n bits. A first voltage divider 27a is inserted before the first A/D converter 2ka, and a second voltage divider 27b is inserted before the second A/D converter 2kb. The data converter 29 converts the output data of the two A/D converters 2ka and 2kb in accordance with the voltage division ratio of the voltage dividers 27a and 27b, and in the figure, the second voltage divider 27b
The number of digits to which the output data of the second A/D converter 2kb is shifted is changed by the set value 1/2K of the voltage division ratio. Note that in FIG. 6, reference numeral 30 is a controller that controls each of the above-mentioned components.

Next, the A/D according to the second embodiment configured in this way
The operation of the conversion circuit 14 will be explained with reference to the flowchart shown in FIG. First, the analog signal from the analog delay circuit 13 is sent to the sample hold circuit 2.
Enter 6. Then, this sample hold circuit 26
samples the above analog input signal and
The value is held for a certain period of time (step ■). next,
The output signal from the sample and hold circuit 26 is input to the first voltage divider 27a, and is set to a predetermined dynamic range corresponding to the number of bits of the first A/D converter 2ka at a fixed voltage division ratio of 1/2i. Ru. Next, the output signal from the first voltage divider 27a is input to the first A/D converter 2ka.

Then, the analog input signal is A/D converted by this first A/D converter 2ka (step 2).

Next, the output data output from the first A/D converter 2ka is input to the controller 30.

Then, the controller 30 reads the digital value of the m-bit output data from the first A/D converter 2ka (step 2). Next, the controller 30 uses the digital value of the output data of the first A/D converter 2ka to control the second A/D converter 2ka so that the analog input signal level to the second A/D converter 2kb reaches the full range. Pressure vessel 2
Set the partial pressure ratio of 7b to 1/2K (step ■). That is, the controller 30 controls the value k that determines the voltage division ratio of the second voltage divider 27b, so that the second A/D converter 2k
control the input signal level of b. Next, the analog signal inputted from the sample hold circuit 26 to the second voltage divider 27b corresponds to the number of bits of the second A/D converter 2kb at the voltage division ratio 1/2' set as above. A predetermined dynamic range is set. Next, the output signal from the second voltage divider 27b is input to the second A/D converter 2kb. Then, the analog input signal is A/D converted by this second 2 kb A/D converter (step 2). Here, it is assumed that the input signal voltages of the first A/D converter 2ka and the second A/D converter 2kb, in which 1 bit is set at the least significant digit, are the same. When the voltage division ratio 1/2' of the second voltage divider 27b is set to =o, when the lowest digit of the first A/D converter 2ka becomes 1, the second A/D converter 2kb will overflow.

Next, the n-bit output data inputted from the second A/D converter 2kb to the data converter 29 is shifted to the higher order digits, and the sample and hold circuit 26 is reset (step 2). Control at this time is performed by control signals sent from the controller 30 to the data converter 29 and sample hold circuit 26, respectively.

Through such an operation, the data converter 29 outputs a (m+n) bit digital signal as a whole. That is, m bits of A
/D converter 2ka and n-bit A/D converter 2
By using kb and (m + n
An A/D conversion circuit 14 having a dynamic range of ) bits is realized. In this embodiment, as shown in FIG. 2 in the embodiment of FIG. 3, the first A/D
Although the S/N sometimes drops once when switching from the converter (line A) to the second A/D converter (line B), such a drop in S/N can be improved.

In addition, in FIG. 6, the partial pressure ratio of the 1 voltage dividers 27a and 27b is shown as 1 which is the power of 2, but the present invention is not limited to this. ), the data converter 29 shifts the digits and converts the effective value to an arbitrary magnification using, for example, a ROM (read-only memory).
The same effect as above can be achieved.

In addition, in FIG. 6, two A/D converters 2k
a, 2 kb, but the present invention is not limited to this. For example, the operation of the first voltage divider 27a and the first A/D converter 2ka is By performing this function using 2 kb of A/D converters, the same function can be achieved with only 2 kb of A/D converters. That is, the second voltage divider 27b
Initially, set the partial pressure ratio 1/2K as = j,
The input analog signal from the sample and hold circuit 26 is converted into a digital signal by the second A/D converter 2kb.6 After that, the controller 30 sets the level of the input signal to the second A/D converter 2kb to the full range. Then, the above value k may be controlled in order to set the voltage division ratio of the second voltage divider 27'b to 1/2.

〔Effect of the invention〕

Since the present invention is configured as described above, the A/D conversion circuit 14 is replaced by the 1 multiplier 22 and the A/D converters 23a, 23.
By configuring the data converter 24 and the data converter 24, the dynamic range of the signal handled can be expanded even if an A/D converter with a small number of bits is used. Therefore, by using A/D converters that are currently in practical use, it is possible to increase the dynamic range of the echo signals handled, and it is possible to easily put the device into practical use. Furthermore, even in pulsed Doppler blood flow measurement in recent ultrasonic diagnostic equipment, according to the present invention, the dynamic range of signals handled by an A/D converter with a small number of bits can be expanded, so a high-speed A/D converter A/D conversion circuit 14 with a large number of bits required for
It is relatively easy to ensure that Therefore, according to the present invention, it is possible to put into practical use an ultrasonic diagnostic apparatus with a biased digital phasing circuit while suppressing high costs.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the ultrasonic diagnostic apparatus according to the present invention, and Fig. 2 shows the principle of the present invention.
FIG. 3 is a graph showing the relationship between the magnitude of the input signal and the magnitude of the output signal for the /D converter.
FIG. 4 is an explanatory diagram showing the operation of the A/D conversion circuit according to the first embodiment, and FIG. 5 is a block diagram showing the first embodiment of the A/D conversion circuit. A graph showing the relationship between the magnitude of the input signal and the magnitude of the output signal for three A/D converters in a modified example of the A/D conversion circuit, and FIG. 6 is a block diagram showing the second embodiment of the A/D conversion circuit. 7 is a flowchart showing the operation of the A/D conversion circuit according to the second embodiment, and FIG. 8 is a block diagram showing an ultrasonic diagnostic apparatus equipped with a conventional digital phasing circuit. 1a to 1n... Vibrator element, 2... Probe, 3
...Pulse generator, 5a-5n...RAM (storage device), 6...Adder, 7...Display device,
12... Control unit, 13... Analog delay circuit, 14... A/D conversion circuit, 21... Detector, 22... Multiplier, 23a, 2ka... First A/D converter, 23b, 2kb...Second A/D converter, 24.29...Data converter, 25...Comparator, 26...Sample hold circuit, 27a...First voltage divider, 27b...
Second voltage divider, 30...controller.

Claims (3)

[Claims] (1) A probe in which a plurality of transducer elements are arranged in a line and transmits and receives ultrasonic waves, and a pulse generator that applies a drive pulse for emitting ultrasonic waves by giving a predetermined delay time to each of the transducer elements. an A/D conversion circuit that converts analog echo signals received by each transducer element of the probe into digital signals; a storage device that sequentially stores digital signals from the A/D conversion circuit; In an ultrasonic diagnostic apparatus comprising an adder that adds data read out from a storage device with a predetermined delay, and a display device that converts the output signal from the adder from D/A to display a tomographic image. , above A/
The D conversion circuit includes a multiplier that varies the dynamic range of the analog echo signal, an A/D converter that converts the analog echo signal whose dynamic range has been varied into a digital signal, and a multiplier that corresponds to the magnification of the multiplier. and a data converter that converts output data of an A/D converter. (2) The magnification of the multiplier of the above A/D conversion circuit is 1/2^k
(where k is an integer), the A/D converter converts it into a binary digital number, and the data converter shifts the output data of the A/D converter by k digits and outputs it. An ultrasonic diagnostic apparatus according to claim 1, characterized in that: (3) The ultrasonic diagnostic apparatus according to claim 1 or 2, wherein the A/D conversion circuit comprises a plurality of A/D converters having different conversion coefficients in parallel. .