JPH01169574A - Vector arithmetic unit - Google Patents

Abstract

PURPOSE:To remove a time for stopping the execution of arithmetic and to attain rapider vector arithmetic by providing the title device with a buffer register for temporarily storing an arithmetic result in a central processing unit. CONSTITUTION:A 1st operand is loaded on a register BF1 in a register file 1 of the vector arithmetic unit 51 and the unit 51 starts a 1st arithmetic operation. The 1st arithmetic result is written in the file 1 and simultaneously written also in the buffer register 8 and a FF 5 is set. Writing in a register 9 is suppressed by a write suppressing signal outputted from a write suppression signal forming circuit 10. When the FF 5 is set, the central processing unit 50 receives the value of the register 8 and then resets the FF 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vector arithmetic device, and more particularly to a vector arithmetic device capable of performing arithmetic processing in parallel with a central processing unit under control from the central processing unit.

Gen Yoshiki' Conventionally, this type of vector arithmetic device has a configuration as shown in FIG. 3 as an example. In FIG. It is a 64-bit wide register. There are two sets of parts that receive operands from the central processing unit 50 (BFl, BF2>, which can receive operands for the next operation in addition to the operation currently being executed. Also, this register file 1
It is assumed that has one system of write addresses and two systems of read addresses.

The operand pointer register (ADl>2) and the operand pointer register (AD2) 3 are registers that indicate the read address of the register file 1.The data read by these operand pointer registers AD1 and AD2 are both input to the arithmetic unit 6. The data read by operand pointer register AD2 is also sent to central processing unit 50.

Register file switching flip-flop Cll0>4
is a flip-flop that serves as an operand receiving buffer from the central processing unit 50 and switches registers BF1 and BF2 of [2] for each operation. When the flip-flop 110 is 0, it is loaded into the register BPI, and when the flip-flop 110 is 1, it is loaded into the register BF2.

The unloadable flip-flop (UNL) 5 is a flip-flop that becomes 1 when the vector arithmetic unit 51 writes the arithmetic result to the register file 1, and becomes 0 when the central processing unit 50 receives the arithmetic result. .

The arithmetic unit 6 is a circuit that performs addition, subtraction, multiplication, division, etc.

The control unit 7 is a circuit that controls setting/holding of various registers, write addresses of the register file 1, arithmetic units, etc.

The operation will now be explained using the following vector operation as an example.

Vi + - Ai This is an operation that is executed continuously for .

When starting the execution of this vector instruction, first the central processing unit 5
0 sends the first set of operands AI and B1 to the register file BF1 of the vector arithmetic unit 51. The vector arithmetic unit 51 starts the first multiplication immediately upon receiving the operand. Following the first set of operands, the central processing unit 50 stores the second set of operands A2 and B2 in register B.
In order to send the result to F2 and receive the result of the first multiplication, it waits for the completion of the calculation by the vector calculation unit 51. When the result of the first multiplication is written in the register file 1 by the vector arithmetic unit 51, the written address is set in the AD2 register 3, and the UNL flip-flop 5 becomes "1". In the central processing unit 5o, the flip-flop 5 is “1”
As a result, the value of the register file addressed by the AD2 register 3 is received, and when the reception is completed, the flip-flop 5 is set to "0". When the flip-flop 5 becomes "0", the vector arithmetic unit 51 sets the operand pointer registers AD1 and AD2 for the next second set of arithmetic operations and starts execution.

In the conventional vector arithmetic device described above, when the vector arithmetic device completes the arithmetic operation and writes the result, and the address of the register file where the arithmetic result is written in the AD2 register 3 is set to logic 1 in the UNL flip-flop 5, This A
Since the central processing unit receives the data of the register file specified by the D2 register 3, the value of the AD2 register 3 cannot be destroyed until the central processing unit has finished receiving this operation result. For this purpose, the vector arithmetic unit is AD2
It is not possible to start an operation by pointing to the next operand address in the register 3. In other words, the vector operation unit cannot perform an operation until the central processing unit receives the operation result and the tlNL flip-flop 5 becomes logic 0. The disadvantage is that it has to be stopped.

OBJECTS OF THE INVENTION An object of the present invention is to provide a vector arithmetic device capable of executing vector arithmetic operations at higher speed by eliminating the time during which arithmetic execution is stopped.

Composition of the Invention According to the present invention, there is provided a vector arithmetic device that is configured to be able to perform arithmetic operations independently of the central processing unit under the control of the central processing unit, and that has a register file that holds its own microprogram and operands. a buffer register for temporarily storing calculation results; selector means for selectively sending the output of the register file and the output of the buffer register to the central processing unit; and data stored in the buffer register. There is obtained a vector arithmetic device characterized in that it includes means for inhibiting writing of the next arithmetic result to the buffer register before the next arithmetic result is transferred to the central processing unit.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Numbers 1 to 7 in the figure are the same as in FIG. 3, and their explanation will be omitted. Operation result storage buffer register (BEBF)
8 sets the calculation result of the vector calculation unit 51 in the register file 1 at the same time, and sends it to the central processing unit 50 6
It is a 4-bit register.

Operation result selection signal flip-flop (BES) 9
sends the calculation results to the central processing unit in register file 1.
from the buffer register (BEBF) F3
This is a register that holds the signal that selects the signal to be sent from the controller, and is determined by the software instruction at the time.

The write inhibit signal generation circuit 1o generates a signal that inhibits writing of the next operation result to the buffer register 8 before the central processing unit receives the data written to the buffer register 8. The details of the circuit are shown in Figure 2.

In FIG. 2, a signal line 101 is a conventional micro10-gram execution inhibit signal in the vector arithmetic unit 51, a signal line 102 is a write instruction signal for the calculation result to the buffer register 8, and a signal fl1103 is an ON [flip-flop This is the output signal of No. 5. Also, 20 is an and gate, 2
1 is an OR gate, and a signal line 104 is a signal for inhibiting writing of the next operation result into the buffer register 8 before the central processing unit receives the previous operation result. signal line 10
Reference numeral 5 denotes a new microprogram execution inhibition signal obtained by ORing the conventional execution inhibition signal 101 and the execution inhibition signal 104 required in this embodiment.

Here, the operation of the multiplication vector instruction will be explained as in the prior art. First, when this vector instruction is started, the BES flip-flop 9 is set to logic 1 based on the operation code, and the value of the buffer register 8 becomes visible to the central processing unit via the selector 11.

Then, the first set of operands AI and B1 is loaded into the register BF1 in the register file 1 of the vector arithmetic unit 51, and the vector arithmetic unit 51 starts the first multiplication. The central processing unit 50 continues to store the second set of operands A2 and B2 in the register BF of the vector arithmetic unit 51.
2 and wait for the result of the first multiplication.

At the same time that the result of the first multiplication is written to the register file 1 by the vector arithmetic unit 51, the buffer register 8
is also written to UNL flip-flop 5. At this time, the signal 102 of the AND gate 20 in FIG.
When there is an instruction to write to the buffer register 9, the output 104 of the AND gate 2o becomes an inhibit signal, and writing to the register file 9 is inhibited. The ADI register 2 and AD2 register 3 each point to the address where the second operand is stored, and the second multiplication is immediately started. Since the UNL flip-flop 5 is set, the central processing unit 50 receives the value of the buffer register 8 via the selector 11 and resets the flip-flop 15. Next, the third set of operands A3 and B3 are loaded into register BF1 and the second result is awaited.

As described in detail, according to the present invention, by providing a buffer register for the calculation results to the central processing unit, the vector calculation unit can perform the next calculation without waiting for the central processing unit to finish receiving the calculation results. Since the vector calculation device can start the calculation, there is no time for the calculation execution to stop in the vector calculation device, and there is an effect that the vector calculation can be performed at a higher speed.

For example, it takes two clock cycles to transfer a 64-bit operation result on a 32-bit data bus, but one operation takes two clock cycles, but a vector instruction that executes many sets of operands in succession takes two clock cycles. , a considerable performance improvement can be expected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of a part of FIG. 1, and FIG. 3 is a block diagram of a conventional vector calculation device. Explanation of symbols of main parts 1...Register file 6...Arithmetic unit 7...Control unit 8...Buffer register 9...Arithmetic Result select signal flip-flop 10...Write inhibit signal generation circuit 11...
·selector

Claims (1)

[Claims] A vector arithmetic unit that is configured to be able to perform arithmetic operations independently of the central processing unit under the control of the central processing unit, and has a register file that holds its own microprogram and operands, and temporarily stores the arithmetic results. a buffer register for transmitting the output of the register file and an output of the buffer register to the central processing unit; and a selector means for selectively sending the output of the register file and the output of the buffer register to the central processing unit; and means for inhibiting writing of the next operation result to the buffer register.