JPH01169945A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01169945A
JPH01169945A JP33366787A JP33366787A JPH01169945A JP H01169945 A JPH01169945 A JP H01169945A JP 33366787 A JP33366787 A JP 33366787A JP 33366787 A JP33366787 A JP 33366787A JP H01169945 A JPH01169945 A JP H01169945A
Authority
JP
Japan
Prior art keywords
tungsten silicide
polycide
insulating film
silicide
polycide structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33366787A
Other languages
Japanese (ja)
Inventor
Akitsu Shimoda
下田 あきつ
Keizo Sakiyama
崎山 恵三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP33366787A priority Critical patent/JPH01169945A/en
Publication of JPH01169945A publication Critical patent/JPH01169945A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain stable forms of electrodes and wirings without being affected by heat treating heat and atmosphere, and improve coating quality of the step-difference of an interlayer insulating film used between wirings, by controlling the shape of polycide structure. CONSTITUTION:A polycide multilayer is constituted by forming an insulating film 2, polysilicon 3 and tungusten silicide 4 on a semiconductor substrate 1. A pattern is formed by spreading photoresist 5 on the upper layer tungusten silicide 4, which is subjected to isotropic etching by using the pattern as a mask. Thereby, a shape having a taper angle at upper corners of the upper tungusten silicide 4 of polycide structure is obtained. Then, anisotropic etching is performed to form a superior polycide structure. Further heat treatment to deposite an insulating film 6 is performed.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は半導体装置の製造方法に関し、特に基板上に形
成したタングステンシリサイドからなるポリサイド電極
及びその配線の形状をその後の熱処理の温度、雰囲気に
かかわらず良好なものにする0 〈従来の技術〉 半導体基板にタングステンシリサイドからなるポリサイ
ド構造をもつ電極及び配線を形成する際、タングステン
シリサイド膜上にエツチングマスクを形成した後、ポリ
サイド構造を得るためにリアクティブイオンエツチング
(RIE )により加工し、その後配線及び電極の表面
を酸化膜からなる絶縁膜で被うために酸素雰囲気中で熱
処理されている。
[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor device, and in particular, the present invention relates to a method for manufacturing a semiconductor device, and in particular, the shape of a polycide electrode made of tungsten silicide formed on a substrate and the shape of its wiring are adjusted to the temperature and atmosphere of subsequent heat treatment. <Conventional technology> When forming electrodes and wiring having a polycide structure made of tungsten silicide on a semiconductor substrate, after forming an etching mask on the tungsten silicide film, in order to obtain a polycide structure, It is processed by reactive ion etching (RIE), and then heat treated in an oxygen atmosphere to cover the surfaces of the wiring and electrodes with an insulating film made of an oxide film.

この時ポリサイド構造なRIEによりエツチングした後
すぐに酸化を行うと、タングステンシリサイドの上方コ
ーナ一部に第2図のようなシリサイドが異常に成長した
はね上がり4aが生じる。
At this time, if oxidation is performed immediately after etching by RIE with a polycide structure, a bulge 4a in which silicide has abnormally grown as shown in FIG. 2 will occur in a part of the upper corner of the tungsten silicide.

なおこの評価はSEMではみられずTEMにより初めて
確認される。
Note that this evaluation cannot be seen with SEM, but is confirmed for the first time with TEM.

同図において、半導体基板1上に絶縁膜2.ポリシリコ
ン3.タングステンシリサイド4が順次積層され、RI
Eによって所望形状に加工した後表面が絶縁膜6で被わ
れている。
In the figure, an insulating film 2. Polysilicon 3. Tungsten silicide 4 is sequentially laminated, and RI
After being processed into a desired shape by E, the surface is covered with an insulating film 6.

〈発明が解決しようとする問題点〉 上記工程を経ることによって生じたタングステンシリサ
イドのはね上がり4aは、ポリサイド構造を配線及び電
極として使用した吻場合、ポリサイド形成後にくり返し
行われる熱処理で形状が不安定になり、配線間の電気的
リークをひきおこす原因になっている。
<Problems to be Solved by the Invention> The bulging 4a of tungsten silicide produced through the above steps can cause the shape to become unstable due to repeated heat treatments after polycide formation when a polycide structure is used as wiring and electrodes. This causes electrical leakage between the wiring.

本発明はポリサイド構造の上部コーナーにできるはね上
がりを抑え、その後の熱処理においても良好なポリサイ
ド構造の形状を維持でき配線間の電気的リークをなくす
ことを目的とする。
The object of the present invention is to suppress the curling up at the upper corner of a polycide structure, maintain a good shape of the polycide structure even during subsequent heat treatment, and eliminate electrical leakage between interconnections.

く問題点を解決するだめの手段〉 半導体基板上に堆積されたポリサイド多層膜を電極及び
配線に形成するエツチング工程において、レジストをマ
スク材としてタングステンシリサイドを膜厚の約1/3
程度等方性エツチングにより除去し、次にRIEにより
ポリサイド構造形成後レジストを除去し所望形状に加工
されたシリサイドの表面を絶縁層で被って形成する。
A solution to the problem> In the etching process for forming electrodes and wiring from a polycide multilayer film deposited on a semiconductor substrate, tungsten silicide is etched using a resist as a mask material to form approximately 1/3 of the film thickness.
The resist is removed by somewhat isotropic etching, and then the resist is removed after forming a polycide structure by RIE, and the surface of the silicide processed into a desired shape is covered with an insulating layer.

く作 用〉 等方性エツチングによってポリサイドの上方コーナ一部
がけずられ、酸化処理時に酸素に晒される環境は従来に
比べて緩和され、コーナ一部でのタングステンシリサイ
ドのはね上りは著しく抑えられる。
Effect〉 A part of the upper corner of the polycide is scratched by isotropic etching, the environment in which it is exposed to oxygen during oxidation treatment is relaxed compared to the conventional one, and the splashing of tungsten silicide at a part of the corner is significantly suppressed. .

〈実施例〉 第1図(C)〜(d)は本発明によるエツチング工程の
実施例を示す。第1図(a)において、半導体基板1上
に例えばドライ酸化により酸化膜からなる絶縁膜2を形
成する。その上に例えば減圧CVDによってポリシリコ
ン3を形成し、更にその上に例えば減圧CVDによって
タングステンシリサイド4を形成し、ポリサイド多層膜
とする。
<Example> FIGS. 1(C) to (d) show an example of the etching process according to the present invention. In FIG. 1(a), an insulating film 2 made of an oxide film is formed on a semiconductor substrate 1 by, for example, dry oxidation. Polysilicon 3 is formed thereon by, for example, low-pressure CVD, and tungsten silicide 4 is further formed thereon by, for example, low-pressure CVD to form a polycide multilayer film.

次に上記ポリサイド多層膜の所望位置に電極及び配線を
形成するため、上層タングステンシリサイド4上にホト
レジスト5を塗布し、これに所定のパターンを形成する
。このレジスト5をマスクに第1図(b)に示すように
タングステンシリサイド4を例えば硝酸20、フッ化ア
ンモン1のフッ硝酸を用いて膜厚500〜100OA程
度(当初厚さ工程度)等方性エツチングを行う。これに
よりポリサイド構造をなす上部タングステンシリサイド
4の上部コーナーにテーパ角を有する形状ができる。次
に第1図(C)のようにタングステンシリサイド及びポ
リシリコンに対してRIEにより異方性エツチングを行
い、良好なポリサイド構造を形成する。マスク材として
用いた酸素雰囲気によるレジストを除去した後上記ポリ
サイド構造を被って第1図(d)の如く絶縁膜6を堆積
するため熱処理が行われる。この状態でタングステンシ
リサイド上部コーナーにはテーパ角があるため、タング
ステンシリサイド中にある余剰シリコンが均一に拡散し
又タングステンシリサイド最表面も酸素に直接ふれる面
積が均等なためポリサイド構造に堆積される絶縁膜は均
一な膜厚で良好な膜質となる。上記工程を経た半導体装
置のポリサイド構造はシリサイドのはね上がりもほとん
どなく、上記エツチング法により、配線抵抗、ダメージ
等実素子への影響が全くないことも確認している。
Next, in order to form electrodes and wiring at desired positions on the polycide multilayer film, a photoresist 5 is applied onto the upper layer tungsten silicide 4, and a predetermined pattern is formed thereon. Using this resist 5 as a mask, as shown in FIG. 1(b), tungsten silicide 4 is isotropically coated with a film thickness of about 500 to 100 OA (initial thickness step) using, for example, 20 parts of nitric acid and 1 part of ammonium fluoride in fluoronitric acid. Perform etching. As a result, the upper tungsten silicide 4 having a polycide structure has a shape having a tapered angle at the upper corner. Next, as shown in FIG. 1C, tungsten silicide and polysilicon are anisotropically etched by RIE to form a good polycide structure. After removing the resist used as a mask material in an oxygen atmosphere, heat treatment is performed to deposit an insulating film 6 covering the polycide structure as shown in FIG. 1(d). In this state, the upper corner of the tungsten silicide has a taper angle, so the excess silicon in the tungsten silicide is uniformly diffused, and the outermost surface of the tungsten silicide has an even surface area that is directly exposed to oxygen, so an insulating film is deposited on the polycide structure. The film has a uniform thickness and good film quality. It has been confirmed that the polycide structure of the semiconductor device that has gone through the above process has almost no silicide splashing, and that the etching method has no effect on the actual device such as wiring resistance or damage.

又、上記実施例によりポリサイド構造がテーパ角を有す
ることで配線間に用いられる層間絶縁膜の段差被覆性が
改善され、その後の工程の短縮にもつながる。
Further, since the polycide structure has a taper angle in the above embodiment, the step coverage of the interlayer insulating film used between the wirings is improved, which also leads to a reduction in the number of subsequent steps.

〈発明の効果〉 以上、本発明によれば、ポリサイド構造の形状を制御す
ることにより、電極及び配線の形状を熱処理温度や雰囲
気にほとんど影響されることなく安定した形状にでき、
また配線間に用いられる層間絶縁膜の段差被覆性を改善
することにより歩留りを向上させ得る。
<Effects of the Invention> As described above, according to the present invention, by controlling the shape of the polycide structure, the shapes of the electrodes and wiring can be made into stable shapes almost unaffected by the heat treatment temperature and atmosphere.
Furthermore, the yield can be improved by improving the step coverage of the interlayer insulating film used between the wirings.

【図面の簡単な説明】 第1図(a)乃至(d)は本発明の方法でエツチングを
行った場合のポリサイド構造の断面図、第2図は従来の
エツチング方法でポリサイド構造を形成し酸化雰囲気で
熱処理を行った場合の断面図である。 1:半導体基板  2:絶縁膜 3:ポリシリコン 4:タングステンシリサイド5:ホ
トレジスト 6:絶縁膜
[Brief Description of the Drawings] Figures 1(a) to (d) are cross-sectional views of a polycide structure when etched by the method of the present invention, and Figure 2 is a cross-sectional view of a polycide structure formed by a conventional etching method and then oxidized. FIG. 3 is a cross-sectional view when heat treatment is performed in an atmosphere. 1: Semiconductor substrate 2: Insulating film 3: Polysilicon 4: Tungsten silicide 5: Photoresist 6: Insulating film

Claims (1)

【特許請求の範囲】 1、半導体基板上に、絶縁層で表面が被われた所望形状
のポリサイドを形成する方法において、半導体基板上の
最上層にタングステンシリサイドを堆積する工程と、 該タングステンシリサイド上にマスクパターンを形成す
る工程と、 露出したタングステンシリサイドを膜厚の途中まで等方
性エッチングする工程と、 等方性エッチングに続いて異方性エッチングを施こして
タングステンシリサイドをエッチングする工程と、 上記タングステンシリサイドを被って絶縁層を形成する
工程とからなることを特徴とする半導体装置の製造方法
。
[Claims] 1. A method for forming polycide in a desired shape whose surface is covered with an insulating layer on a semiconductor substrate, comprising: depositing tungsten silicide on the top layer on the semiconductor substrate; and on the tungsten silicide. a step of isotropically etching the exposed tungsten silicide to the middle of the film thickness; a step of etching the tungsten silicide by performing anisotropic etching following the isotropic etching; A method for manufacturing a semiconductor device, comprising the step of forming an insulating layer covering the tungsten silicide.
JP33366787A 1987-12-24 1987-12-24 Manufacture of semiconductor device Pending JPH01169945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33366787A JPH01169945A (en) 1987-12-24 1987-12-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33366787A JPH01169945A (en) 1987-12-24 1987-12-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01169945A true JPH01169945A (en) 1989-07-05

Family

ID=18268620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33366787A Pending JPH01169945A (en) 1987-12-24 1987-12-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01169945A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5698072A (en) * 1992-06-29 1997-12-16 Sony Corporation Dry etching method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5698072A (en) * 1992-06-29 1997-12-16 Sony Corporation Dry etching method
US5880035A (en) * 1992-06-29 1999-03-09 Sony Corporation Dry etching method

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