JPH01170286A - Multiplex transmission signal reproducing device - Google Patents

Abstract

PURPOSE:To receive and reproduce a signal stably in case of multiplex transmission of other signal on a signal subject to amplitude modulation by providing plural delay circuits retarding a time corresponding to repetition and providing an arithmetic circuit adding and subtracting outputs of the plural delay circuits. CONSTITUTION:In order to demodulate an audio signal subject to digital coding, and output of a frequency conversion circuit 3 is given to a band pass filter 14, where a voice signal band subject to multiplex transmission an digital coding is selected, the signal is amplified, and a synchronizing detecting circuit 15 uses the signal reproduced by a carrier reproducing circuit 16 and synchronously with the carrier to detect and demodulate the signal modulated by component orthogonal to the amplitude modulation component of the carrier. The demodulated waveform and another demodulation waveform subject to one horizontal period delay via a delay device 17 are subtracted by a subtractor 18, then white level noise is increased by 2<0.5> times only because of the presence of random property thereby improving the S/N. In case of the transmission of same signal in opposite phase for each prescribed period, since the calculation circuit applies subtraction after a prescribed period of delay, the disturbance caused at a prescribed period of interval is calculated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multiplex transmission system, and particularly to a multiplex transmission system that receives a transmission signal effective for multiplexing and transmitting digitally encoded audio and the like on a video signal. The present invention relates to a signal reproducing device.

[Conventional technology]

Methods for multiplexing digitally encoded PCM audio and video signals are reported in Satellite Broadcasting Receiving Technology Study Group Report Part 11, "Satellite Broadcasting Receivers," edited by the 4-Wave Technology Association, published in June 1981. However, the current NTSC movie 1#! PC using 5.7272 h subcarrier for signal
Since M audio is multiplexed, it does not meet the bandwidth of current terrestrial television broadcasting, making it difficult to use for terrestrial television signals.

On the other hand, the possibility of multiplex transmission for current terrestrial television broadcasting is described on page 205 of Broadcasting Technology Book 2 "Broadcasting Systems" edited by the Japan Broadcasting Corporation, published by the Japan Broadcasting Publishing Association in January 1981. However, there was no description of a method that could secure a transmission capacity of about 1M pits/second to transmit two channels of high-quality audio.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not have a method for multiplex transmission of high-quality audio signals in the current terrestrial television broadcasting.

An object of the present invention is to provide a reproducing device for stably receiving and reproducing other signals when multiplexing the amplitude modulated signal with those signals, and to provide a reproducing device for stably receiving and reproducing the amplitude modulated signal. It is an object of the present invention to provide a multiplex transmission signal reproducing device that is effective for stably receiving and reproducing a transmission system that transmits multiple signals such as high-quality digitally encoded audio signals.

[Means for solving problems]

The above purpose is equivalent to repeating a multiplexed signal that is transmitted repeatedly K a 6 times every certain period in a receiver that demodulates a multiplexed signal that is multiplexed and modulated by giving an orthogonal relationship to an amplitude-modulated carrier wave. This can be achieved by providing multiple circuits for time delay 'M#, and by providing an arithmetic circuit and a memory circuit for adding and subtracting the outputs of the plurality of delay circuits.

[Effect]

Since the signal delayed by the delay circuit is added and calculated by the arithmetic circuit, the same signal is added due to the delay, and if it is repeated twice, the signal amplitude will increase by two times, but since white noise has randomness, it will only increase by J times. Therefore, the signal-to-noise ratio of the received and reproduced signal can be improved. Furthermore, when transmitting the same signal in reverse phase every certain period of time, the pressure is subtracted in the arithmetic circuit after a certain period of delay, so that disturbances occurring at certain intervals can be canceled out and removed.

In particular, when multiplexing signals by giving the video signal carrier wave an orthogonal relationship to the video signal, the same multiplexed signal can be transmitted in reverse order in adjacent horizontal scanning periods over multiple even-numbered horizontal scanning periods, such as two horizontal scanning periods. When the pressure is transmitted in phase, the multiplexed signals with a time difference of one horizontal scanning period delay are the same and have opposite phases, so the delay circuit delays the time by a multiple of one horizontal scanning period, and the arithmetic circuit delays W! The signal transmitted during the I-contact horizontal scanning period is subtracted. As a result, the multiplexed signal has an amplitude 20 times larger, and interference such as leakage or ghosting from the video signal is determined by the correlation of each horizontal scanning period of the video signal (vertical correlation on the TV 17 screen). cancel.

〔Example〕

Below, as a simple example of the receiver of the present invention, an example in which digitally encoded audio signal tube multiplex transmission is transmitted to the current terrestrial broadcasting television channel will be shown in Part 1.

1 is an antenna, 2 is a high frequency amplification circuit, 5 is a frequency conversion circuit, 4 is a reproduction IP filter for the receiver, 5 is an intermediate frequency amplification circuit, 6 is a video signal intercept circuit, 7 company video signal amplification circuit, 8 is a color difference signal demodulation circuit, 9 is a primary color signal demodulation circuit, 10
is a cathode ray tube, 11 is an audio intermediate frequency amplification circuit, 12 is an audio FM detection circuit, 13 is an audio signal output terminal, 14 is a band pass filter, 15 is a synchronous detection circuit, 16 is a carrier wave regeneration circuit, 17.201 is a delay circuit, 18 is a subtracter, 20 is a storage circuit, 21 is a timing regeneration circuit, 22 is a code identification circuit, 23 is a clock regeneration circuit, 24 is a digital signal processing circuit, 25 is a digital-to-analog conversion circuit (hereinafter abbreviated as DAC), 26 200 is an output terminal for a digitally encoded and transmitted audio signal, and 200 is a synchronization detection circuit.

A television signal input from an antenna 1 is amplified by a flat frequency amplifier circuit 2, frequency-converted to an intermediate frequency for demodulation by a frequency conversion circuit 3, passed through a reproduction IP filter 4 for a receiver, and then transmitted to an intermediate frequency amplifier circuit 5. Amplify. Tuning is performed by changing the local oscillation frequency of the frequency conversion circuit 3. The video signal band from the signal amplified by the intermediate frequency amplification circuit 5 is detected by the video signal detection circuit 6, and a primary color signal is obtained from the luminance signal output from the video signal amplification circuit 7 and the color difference signal output from the color difference signal demodulation circuit 8. The demodulation circuit 9 obtains the three primary colors of 几, G, and B, and displays them on the cathode ray tube 10.

On the other hand, the audio signal band is amplified by the audio intermediate frequency amplification circuit 11 and detected and demodulated by the audio FM detection circuit 12 to obtain an audio signal at the audio signal output terminal 13.

The above is the same as a conventional television receiver.

In addition to the above, in order to demodulate the digitally encoded audio signal, the output of the frequency conversion circuit 3 is selected and amplified by the digitally encoded audio signal band multiplexed and transmitted by the bandpass filter 14, and the synchronous detection circuit In 15,
Using a signal synchronized with the carrier wave reproduced by the carrier wave regeneration circuit 16, a signal modulated with a component orthogonal to the amplitude modulation component of the carrier wave is detected and demodulated.

A subtracter 18 subtracts the demodulated waveform from the demodulated waveform that has passed through the delay device 17 and is delayed by one horizontal period. By subtracting, the transmitted data is doubled and the white noise is only increased by a factor of 4. Furthermore, interference from images that have a high correlation in each horizontal period, such as the video 1-coast, can be canceled out and removed. Subtractor 1
The signal obtained in step 8 is converted into a digital code using a code identification circuit 22 and a clock recovery circuit 23 at a point with a low error rate (the so-called maximum opening of the eye pattern).

The synchronization signal detection circuit 200K detects synchronization signals such as vertical synchronization and horizontal synchronization of the video signal and sends them to the timing reproduction circuit 21, thereby facilitating generation of control timing waveforms for the storage circuit 20. The delay circuit 201 is provided to absorb the difference in delay time between the horizontal video placement circuit 6 and the code identification circuit 22. A storage circuit 20 is controlled by a timing regeneration circuit 21 to store only necessary data out of the digitally encoded signal, and to restore the original data transmission rate when read out. After that, the digital signal processing circuit 2
In step 4, error detection and correction is performed using an error detection and correction code that occurs during transmission. DA the digital signal after error detection and correction
C25 converts it into an analog signal and returns it to an audio signal, which is then output to an output terminal 26 for digitally encoded audio signals.

Note that interference removal from the video signal is performed in the following process. If data X is sent at a certain timing in a certain horizontal scanning period, the same data X is sent at a certain timing in the next horizontal scanning period with a delay of one horizontal period.
The inverted X data is sent. Receiver delay device 17
The subtracter 18 subtracts the X received one horizontal scanning period before and the X received in the next horizontal scanning period at the same timing, so X - (X) = 2X, and twice the signal is obtained. . If the video signal is subject to G interference during this transmission, the video signal will have a high correlation in each horizontal scanning period il! ill (m-jima etc. picture 1
In this case, q will be interfered with both at the timing of X and at the timing of X. By the subtractor 18, (X+G) - (X+(f) = 2

According to the present embodiment described above, there is an effect that interference from images can be reduced.

FIG. 2 shows an example of a transmitter of the present invention that generates the signal transmitted by one embodiment of the receiver described above. 31 is an audio signal input terminal, 32 is an FM modulator, 35 is an audio signal carrier generator, 3
4 is a video signal input terminal, 35 is a matrix circuit, 36
11ll1 signal processing circuit, 57 a color difference signal processing circuit, 38 an addition circuit, 39 a video converter, 40 a video signal carrier generator, 41 an input terminal for audio 1H signal to be digitally encoded and transmitted; 42 is an analog-to-digital converter (hereinafter abbreviated as ADC), 43A is a digital signal processing circuit, 43B is a processing circuit, 44 is a low-pass filter,
45 is a phase shifter, 46 is a modulator for digitally encoded audio signals, 47 is an adder, 48 is a transmission V8B filter for residual side wave amplitude modulation, 49 is an adder, 50 is an antenna, 462 is an equalizer It is.

An audio signal from an audio signal input terminal 31 is used to FM-modulate the audio carrier wave from an audio signal carrier generator 33 in an M modulator 32 . R input to barking input Mizuko 34
, QB are divided into a luminance signal and a color difference signal by a matrix 55, processed by a luminance signal processing circuit 56 and a color difference signal processing circuit 37, and then added by an adder 38. The carrier wave from the video signal carrier generator 40 is modulated by the signal after the addition using the video modulator 39, the transmission VSB filter 48 limits the band to the television broadcast band, and the adder 49 adds it to the audio signal. It is transmitted from the antenna 50.

The above is the same as conventional terrestrial television broadcasting. Add the following to transmit high-quality audio to the above signals.

Add the audio signal to be multiplexed to the input terminal 41, and send the audio signal to A.
A DC 42 converts the signal into a digital signal, and a digital signal processing circuit 43A adds a code for detecting and correcting errors occurring during transmission and performs interleaving processing. The processing circuit 43B performs processing that is repeated multiple times per horizontal scanning period, and in adjacent horizontal scanning periods, data is inverted and transmitted in reverse phase. Detailed explanation in section 5.10.13
Use diagrams, etc. Thereafter, unnecessary high-frequency components are removed through a low-pass filter 44 suitable for the output transmission rate of the processing circuit 43B. With this digitally encoded audio,
The video signal carrier wave shifted by 90 degrees via the phase shifter 45 is modulated by the digitally encoded audio signal modulator 46, and the frequency is modulated by the equalizer 462, which has characteristics inverse to the Nyquist filter with a video amount of 1 NIP. Correct the characteristics and adder 47
is added to the carrier wave modulated by the video signal. the result,
The video carrier wave is modulated in an orthogonal relationship with the video signal and the digitally encoded audio signal.

FIG. 5 shows the modulated spectrum, and FIG. 4 shows a vector diagram of the modulation state of the video signal of the video carrier wave and the digitally encoded audio signal.

51 in FIG. 5 is the spectrum of the video signal after the VSB filter, 52 is the spectrum of the audio signal subjected to FMR#4, 5
3 shows the spectrum of a 31C digitally encoded audio signal. Here, since the video signal spectrum 51 and the digitally encoded audio signal spectrum 52 are orthogonally multiplexed, they are shown divided into two stages in the third factor. Furthermore, the spectrum of the digitally encoded audio signal is shown when the carrier wave is modulated at a transmission rate of IM bits/second and a transmission roll-off rate of 1L5. In the third factor, −α75MF1z for the video carrier
The following spectrum is reduced by a V8B filter with vestigial sideband amplitude modulation.

Up to 42 Mn2, the video signal has a spectrum in the vicinity of 4.5 h/klz where the audio carrier wave is FM'R modulated. ±0.75M for video transport tliK (since both sidebands are transmitted for z, the general amplitude variation tJ
You can think of it as I4 (DSB). If a signal within ±α75 M(z) is made to correspond to the digital code 1 and modulated with amplitudes A and -A, the vector of the carrier wave is orthogonal to the carrier wave having both sidebands. If , costs c t fA sin・Ct
11). Here, -C is the angular frequency of the carrier wave.

Expanding equation 11), we now consider interference from a digitally encoded audio signal to a received 1M video signal. picture! 'No. Ogi Circuit is c
For os*ct, which is covered by J191, regardless of the value of A, only the coefficient of cos*ct (that is, only the video signal) is reproduced and does not cause interference.Also, when the video signal detection circuit detects the envelope If the detector is busy, interference can be reduced by lowering the value of A below 1.For example, if A is α1, Jr77=toos, which means that the signal is o and oos compared to 1 (approximately -40 dB).
However, if the SN ratio of the video signal is 40 dB or more, there is no problem in practical use.

On the other hand, interference from the video signal to the digital signal and the audio is transmitted by the synchronous detection circuit 15 as shown in FIG. This can be eliminated by demodulating only the orthogonal components. Considering the signal level to noise ratio (hereinafter referred to as SN ratio) K, if the SN ratio of the video signal is 40 dB at a practical level,
The bandwidth is the transmission band of the digitally encoded audio ig signal +
Since it is about four times as large as fi I MHz, the SN ratio of the digitally encoded audio signal is 46 dB, but if the modulation level A is α1, the transmission SN ratio is about 26 dB. Also, when considering the relationship between the S/N ratio and bit error rate of a digital signal for a general binary signal, the 8N ratio is 17
．． It is 10 at 4 dB. The 8N ratio of the video signal is 40d
In the case of B, the transmission SN of the digitally encoded audio signal
The ratio is 26dB, making it practical for transmitting digital signals.

This is a sufficient value.

Here, a specific example of the processing circuit 43B in FIG. 2 is shown in FIG. Further, FIG. 6 shows an explanation of the operation of FIG. 5 and an example of the transmission data string of the present invention. 60 is an input terminal, 61 is a time axis compression circuit, 62 is a timing generation circuit, 63 is an inverter, 64 is a delay circuit, 65 is a changeover switch, 66 is an output terminal, 67 is a data string of input terminal 60, 68 is a time axis The output data string of the compression circuit 61, 69 is the output data string of the delay circuit 64 that has passed through the inverter 63 and the delay circuit 64, 70 is an example of the transmission data string of the present invention, and 71 is timing shaping.

A data string 67 applied to an input terminal 60 is subjected to time axis compression by a time compression circuit 61 according to the timing of a timing generation circuit 62, and is converted into intermittent data shown in a data string 68. When this intermittent data is inverted by an inverter 65 and a delay circuit 64 and delayed by a delay time T, that is, by 5 data in the example of FIG. 6, a data string 69 is obtained. When the data string 69 and the data string 68 are added using the changeover switch 65, a data string 70 is obtained. This data string 70 is obtained by delaying and inserting the same data that is inverted during the dataless period of the data string 68. FIG. 7 shows an example of a transmission pattern of the present invention. The delay time t is set to be the same as the horizontal scanning period of the video, and timing shaping 7 is performed.
1 is assumed to be synchronized with the horizontal synchronization signal of the television receiver, and the data transmission timing is simulated in accordance with the television 17 screen.

In Figure 7, the horizontal axis indicates the horizontal scanning direction and the vertical axis indicates the vertical scanning direction. The time series data from 41 to 4 in the first horizontal scanning period becomes inverted data from 61 to 4 in the second horizontal scanning period, and becomes the same data with opposite phases in the first and second horizontal scanning periods. Become.

Also, consider here the video color subcarrier of current television broadcasting. FIG. 8 shows a vector diagram of color subcarriers immediately above the video carrier. (4) shows the case where there is no multiplexing on orthogonal components of the video carrier wave, and (b) shows the case where there is multiplexing on the orthogonal components. -8 indicates the phase rotation in the color subcarrier, -8 and -8
' indicates that the phase of the color subcarrier due to adjacent horizontal scanning periods is shifted by X. 2 to S indicate the change process of the vector of the color subcarrier, and 41%8 and 1' to S' indicate that the phase of the color subcarrier is shifted by an amount. Furthermore, KA and -A indicate multiplexed signals into orthogonal components, and indicate a case where, at a certain point in time, the signal becomes KA and -A in adjacent horizontal scanning periods. In current television broadcasting, due to the relationship between the frequency of the color subcarrier and the number of horizontal scanning periods, the color subcarrier is 41.5 times larger in adjacent horizontal scanning periods.
m, n, o ・*, s and j! ', m', n
The phases are shifted by I as shown by ', o'..., S'. When multiplexing to the quadrature components is performed as shown in Fig. 8(b)K, phase fluctuations of the video carrier wave are caused as shown in Fig. 4, and when the television video signal detection method is envelope detection. , A, the maximum amplitude of the color subcarrier appears between S and 1, resulting in a position difference φ from the maximum amplitude phase difference in the case of no orthogonal components. The phase variation of the color subcarrier appears as a hue change on the reproduced video screen. This phase fluctuation is caused by cos*c in the figure when the horizontal video signal method is used and the synchronous detection method is used.
Since only the direction component of A is detected, the maximum amplitude phase of the color subcarrier is 1 even if A is multiplexed, and no phase fluctuation occurs. In the case of envelope detection, two and m- depending on the sign of the multiplexed signal.
When the orthogonal components are multiplexed to (indicated by A and -A in Figure 8), the phase direction (phase lead and lag) of the maximum amplitude of the color subcarrier is determined, and the amount of phase fluctuation is determined by the absolute value of A and one person. It's decided. When the phases of the multiplexed signals are set to A and -A in adjacent horizontal scanning periods, the directions of phase fluctuations of 411S and 18' become opposite directions and the amounts of phase fluctuations become the same, as shown in FIG. 8(b). The change in hue of the screen in adjacent horizontal scanning periods with the same signal is reversed, making it possible to perceive the change in hue due to the frequency characteristics of the chromaticity sensitivity of human vision (integral effect of the eye).

That is, 41-85 and 41-as in Figure 7,
Between the horizontal scanning period in which opposite phases of the same data are included, such as bl~b5 and b1~5-, the multiplexed signals are used in reverse, such as A and -A, so it is difficult to perceive a change in hue. . However, in horizontal scanning periods such as a1 to as and bt to bs, where the same data is not in reverse phase, a hue change is easily felt.

Furthermore, in television receivers that employ a "<C-shaped filter" with horizontal scanning period correlation (so-called line correlation) to separate luminance signals and color signals, phase fluctuations of color subcarriers are caused by the circuit. Can be offset. FIG. 9(4) shows a configuration diagram of a comb-shaped filter for extracting a color signal in a general luminance No. 15 color signal separation, and FIG. 9(b) shows a waveform diagram for explaining the operation. 80 is an input terminal, 81 is a delay circuit, 82 is a subtracter, 83 is an output terminal, and 84 to 87 are color subcarrier waveforms. 84 is the case where there is no multiplexing, 85 is the right side of FIG. 8(b), 86 is the left side of FIG. 8(b), and 87 is the inversion of 860. The color subcarrier in the case of no multiplexing is shown as a waveform 84 with maximum amplitude at time 1 corresponding to (-) in FIG. When the multiplexed signal A is added here, the maximum amplitude is shifted between 3 and 1, resulting in waveform 85. Further, in the next adjacent horizontal scanning period, the -A multiplex signal is added, and the 18' color subcarrier has a maximum amplitude phase between p' and q', resulting in a waveform 86. Delay circuit 81
After that, waveform 85 and waveform 86 delayed by one horizontal scanning period are applied to subtracter 82 . Although the inversion of waveform 86 is shown as waveform 87, subtracting waveform 86 from waveform 85 is equivalent to waveform 85.
The waveform 86t is added to the waveform 86t, and the amplitude is further increased by 17
2 results in waveform 84. This waveform 84 is the output terminal 85
obtained from. This shows that the color subcarrier obtained by the rhombic filter does not undergo phase fluctuation even if the video signal detection method is envelope detection and multiplexed signals are added. Show a1~alt and a1
~ 6g, the phase fluctuation is not affected only when processing horizontal scanning periods in which the upper and lower data have opposite phases in adjacent horizontal scanning periods, so horizontal scanning that does not undergo phase fluctuations for each horizontal scanning period. A period appears.

As shown above, according to the embodiment of the present invention shown in FIGS. 5 to 7 in addition to FIG. This has the effect of reducing interference caused to

In FIG. 5, the input data is continuous data, so the time axis compression circuit 61 is used, but it may not be necessary if the input data is intermittent discontinuous data.

Next, another specific example of the processing circuit 43B shown in FIG. 2 is shown in FIG. Further, FIG. 11 is a diagram for explaining operations such as an example of a transmission data string of the present invention, and FIG. 12 is an example of a simulated pattern of transmission data of the present invention. 90 is an input terminal, 91 is an inverter, 92 is a delay circuit, 93 is a timing generation circuit, 9
4 is a changeover switch, 95 is an output terminal, 96.101 is a timing waveform within the timing generation circuit 93, 97 is an input data string, 98 is an output data string of the delay circuit 92, 99
is the timing generation circuit 93 output timing waveform, 100
is an example of a transmission data string of the present invention.

The data string 97 applied to the input terminal 90 is transferred to the inverter 9
1 and is delayed by a delay circuit 92 to obtain a data string 98. Note that the timing waveform 96 is inverted at time T. The timing waveform 99 is inverted during the data period in the data string, and when it is on the upper side in the figure, the changeover switch 94 is inverted.
When it is on the (a) side, it touches on the (b) side when it is on the lower side. A data string 100 is obtained at an output terminal 95 by the changeover switch 94 controlled by this timing waveform 99.

FIG. 12 is a diagram schematically showing a data string 100 in accordance with a television screen using a timing waveform 101 as a horizontal synchronizing signal. The lateral force horizontal scanning direction is the longitudinal 4C vertical scanning direction. As shown by the circle frame in FIG. 12, in adjacent horizontal synchronizing signals, the top and bottom of each data are inverted.

Inverting data in adjacent horizontal scanning periods indicates that the multiplexed signals to the orthogonal components of the video carrier wave have an opposite phase relationship, and the effect of reducing the interference to the hue change of the video due to the multiplexed 1g signal is This is the same as the explanation in Figures 8 and 9.

As described above, according to the embodiments shown in FIGS. 10 to 12 in addition to FIG. 2, since the multiplexed signals in adjacent horizontal scanning periods have opposite phases, it is possible to reduce the interference that affects the hue change of the video. be. In addition, in all horizontal scanning periods, each piece of data has an inverse phase relationship with the adjacent scanning period, and the cancellation of hue changes becomes a mesh pattern as shown by the round frame in Figure 12, so the disturbance to hue changes becomes finer. , due to the low sensitivity range tlld of the chromaticity of the visual sense, it is possible to further reduce the disturbance to the hue change of the image than in the case of FIGS. 5 to 7.

In the above embodiment, the case of odd number data was shown as an example of 7 data in one horizontal scanning period as the transmission data string, but in the case of even number data, 6 data is taken as an example and shown in FIGS. 13 to 15. FIG. 13 shows a concrete example of the processing circuit 43B of FIG. 2. FIG. 14 is a diagram for explaining operations such as an example of a transmission data string, and FIG. 15 is an example of a simulated pattern of transmission data of the present invention. hi is a timing generation circuit, 102 is a timing input terminal, 103 is a timing generator, 104, 10
7, 110 is a timing waveform within the timing generation circuit 93, 105 is an input data string of the input terminal 90, 106 is an output data string of the delay circuit 92, 108 is a timing waveform of the output of the timing generation circuit 93, and 109 is the present invention. An example of the transmission data string 111 is an exclusive OR (hereinafter abbreviated as EOR). In addition, the same symbols as in FIG. 10 indicate the same functions.

The difference with Fig. 10 is that an exclusive OR 111 is provided inside the timing generation circuit, and the timing waveforms are 104° and 1.
07, the timing waveform 108 is obtained at the output of the timing generation circuit 1, and the changeover switch 94 is controlled. EOR1ll is for reversing the control switch 94 for each horizontal scan interval M, and the transmission data string 109 is obtained, and the transmission data shown schematically in FIG. 15 is displayed on the television 217 screen. It becomes a pattern.

In the above embodiment as well, multiplexed 11N
This has the effect of reducing the interference caused by signals to changes in the hue of images.

Here, the delay circuit 17, subtracter 18, memory circuit 20 . The timing recovery circuit 21 will be explained in detail.

FIG. 16 shows a specific example of the storage circuit 20 and timing regeneration circuit 21 of the 'aI tone circuit which receives the transmission data string 70. Moreover, FIG. 8g17 is an explanatory diagram of the operation.

505 is a frame synchronization signal input terminal, 306 is an input terminal for inputting No. 1 data synchronization obtained by the clock regeneration circuit 25, 307 is a horizontal synchronization signal input terminal, 308° is a data string input terminal, and 509 is demodulated digital data. Column output terminals, 510, 318, 521, 536 are 2 frequency dividers,
311°312.313.514,523,327,5
37 is latch, 315,5115°522.335,5
54 is an inverter, 317 is a NAND gate, 319,
335 is a shift register, 520 is an AND gate, 52
5 and 526 are kakuntas, 328 is a decoder, 529° and 330 are changeover switches, 331 and 552 are temporary storage circuits (hereinafter abbreviated as RAM), 17 is a delay device, and 18 is a subtracter.

Further, 350 is a timing waveform for frame synchronization, 351
is a timing waveform for horizontal synchronization, 352 is a timing waveform for synchronizing received data, 353 is a receiving 1g data string, 554 is an output data string of the delay circuit 17, 555 is an output data string of the subtracter 18, and 356 is an output of the shift register 335 Data string, 357 is the output waveform of the frequency divider 318, 358 is the output waveform of the shift register 319, 359 is the output waveform of the AND gate 520, 560 is the output waveform of the frequency divider 310, 361 is the output waveform of the latch 311 , 362 is latch 3
12 output waveform, 363 output waveform of latch 313, 5
64 is the output waveform of the NAND gate 517, 365 is the output waveform of the latch 314, 366 is the initial state of the write address generated in the kakunta 326, and 367 is the kakunta 326
The write address generated in 368 is the decoder 328
369 is the output waveform of latch 327, 372
is the read address generated by Kakunta 325, 3
75 is the output waveform of the frequency divider 336, and 574 is the latch 33.
This is the address of the output data of No.7.

Data string 353 received from data string input terminal 308
is delayed by one horizontal scanning period by the delay device 17 and becomes a data string 3541c. The data string 353 is subtracted from the data string 554 by the subtracter 18, and the output thereof is binarized by the code identification circuit 22 and the clock recovery circuit 23.
is obtained. If data string 355 is shifted twice by shift register 335 at the falling edge of shaping 552, data string 556 is obtained. In the data string 356, the 0 symbol indicates necessary data other than a1 to 6g, and the X symbol indicates unnecessary data. A waveform 357 obtained by dividing the horizontal synchronization timing waveform 351 inputted from the horizontal synchronization signal input terminal 307 by two using a frequency divider 318 is shifted twice at the falling edge of the waveform 352 by a shift register 319 to obtain a waveform. Get 358.

Waveform 358 and waveform 352 are passed through AND gate 320 to obtain waveform 359. Frame synchronization signal input terminal 505
The timing waveform 550 for frame synchronization input from
A waveform 360 obtained by dividing the frequency by two by a frequency divider 310 is latched by a latch 311 at the falling edge of a waveform 352 to obtain a waveform 361. Shape 35 the waveform 361 with the latch 312
Latch at the falling edge of 2 to obtain waveform 362.

Waveform 563 and waveform 551 obtained by latching waveform 360 at the falling edge of waveform 351 with latch 513
A waveform 364 is obtained through the NAND gate 317.

The first falling edge of waveform 364 presets latte 314 to obtain waveform 365.

A write address 367 is generated by inputting a waveform 359 as a clock signal and a waveform 365 as an enable signal to the counter 326 . However, the counter 525.5
When the input signals of the enable terminals P and T of No. 26 are in L panic, the enable state is established. Note that the initial state of the write address is 566K as shown. Write address rN-1
J is decoded by the decoder 328 and the resulting waveform 368 is latched at the falling edge of the waveform 559 by the latch 327.
A waveform 369 is obtained by latching. If the waveform 569 is used as the clear signal for the counter 326, the counter 326 will become "0".
” to “N-IJ write addresses are generated. However, the counter 326 is of a synchronous clear type such as LS161.
Write to A M 551.552.

In addition, waveform 352 is divided by 2 using frequency divider 521 to form waveform 57.
Get 0. Waveform 369 is latched by latch 323 at the rising edge of waveform 370 to obtain waveform 371. If we input the waveform 370 as the clock signal of the counter 325 and the waveform 371 as the clear signal g, we get
A read address shown at 672 can be generated. The waveform 352 is inverted by the inverter 333, and the frequency thereof is divided by two by the frequency divider 336 to obtain the waveform 673.

Read address 572K Therefore RAM 531.5
The data string read from 52 is latched by the latch 337 at the rising edge of the waveform 373 to output the data string 374.
get. Input the waveform 362 to the control terminals S of the changeover switches 529 and 330 and the wg terminal of the RAM 332, and
Input the reverse phase signal of waveform 362 to the WE terminal of iV1331, and control the changeover switches 329 and 330 so that the control signal of the terminal S is connected to the A# side when it is Low, and to the KB side when it is High. 1 (, A Al 325 and 几Al~f 526. can be used by switching between read and write in an rC seesaw pattern every 2 frames.However, 几A
Input of Iku terminal of 14525, 526 (i! No. is Low
It shall be in the write state in the case of .

According to this embodiment, the transmission data string 70 shown in FIG. 6 can be demodulated, and as explained in FIG. 1, interference from the video signal can be reduced.

Note that depending on the initial condition of the divider 518 when one source is turned on, the divider output such as the waveform 557 may be inverted and unnecessary data may be processed. It is possible to obtain a necessary waveform such as waveform 357 by a method such as setting 9 by the output.

FIG. 18 shows a specific example of the memory circuit 20 and timing regeneration circuit 21 of the demodulation circuit that receives the transmission data string 100 shown in FIG. 11.

However, the number of data in the transmission data string 100 in Fig. 11 is 1.
In the horizontal scanning period, there were 7 pieces, but in this embodiment, it was set to 5 pieces. There is no difference in the fact that the number of data within one horizontal scanning period is an odd number.

Components with the same symbols as in FIG. 18 indicate the same functions. Also the first
FIG. 9 is an explanation of the operation of FIG. 18. 380, 587 are 2 frequency dividers, 581.382, 384, 393.594,
396 is a latch, 383.395 is a shift register, 3
85, 388, 389, and 392 are inverters, and 386 is a NAND gate. Further, 400 is a timing waveform for frame synchronization, 401 is an output waveform of the frequency divider 380, and 4
02 is the output waveform of the latch 381, 405 is the timing waveform for horizontal synchronization, 404 is the output waveform of the NAND gate 386, 405 is the output waveform of the latch 382, 406 is the timing waveform for data synchronization, 407 is the received data string, 408
is the output data string of the delay device 17, 409 is the output data string of the subtracter 18, 410 is the output data string of the shift register 595, 411 is the output waveform of the shift register 383, 41
2 is the output waveform of the divider by 2 391, 413 is the initial state of the write address, 414 is the write address, 415 is the output waveform of the decoder 328, 416 is the output waveform of the latch 594, and 417 is the output waveform of the divider by 2 390. , 418 is the output waveform of the latch 395, 419 is the read address, 42
0 is the output data string of latch 396, 421 is latch 38
4 is the output waveform of the frequency divider 387, and 422 is the output waveform of the frequency divider 387.

The received data string 407 is delayed by one horizontal scanning period τ due to the delay 417 and becomes the data string 40B. Data string 407 is subtracted from data string 408 and converted into a digital value by clock recovery circuit 23 and code identification circuit 22. Data string 409 is then shifted three times by shift register 395 at the falling edge of waveform 406 to obtain data string 410. obtain. In the data string 410, the 0 symbols are e1 to el, f+
, h indicates necessary data, and the X symbol indicates unnecessary data. The waveform 405 is shifted 5 degrees by the shift register 383 at the falling edge of the waveform 406 to obtain a data string 411. Waveform 406 is divided by 2 using frequency divider 591 to obtain waveform 41.
Get 2. Counter 526 inputs waveform 412 as a K clock signal and as an enable signal to obtain write address 414. The initial state of the write address is 4.
As shown in 13. Waveform 41 obtained by decoding write address rN-1J from decoder 328 button
5 is latched by latch 394 at the falling edge of waveform 412 to obtain waveform 416. If the waveform 416 is used as a clear signal for the counter 326, the counter 326 will change from "o" to
"Generate write address of N-IJ. Data string 41
Write 0 to RAM 325,3 by write address 414
I pledge to the 26th. Waveform 406 is inverted by inverter 588 and divided into two by frequency divider 590 to obtain waveform 417. Waveform 416 is latched by latch 393 at the falling edge of waveform 417 to obtain waveform 418. A read address 419 is generated by inputting the waveform 417 as a clock signal and the waveform 418 as a clear signal to the counter 325. The data string read from the RAMs 531 and 332 by the read address 419 is latched by the latch 396 at the falling edge of the waveform 412 to obtain an output data string 420. Waveform 418 is obtained by latching the rising edge of waveform 412 with latch 384.

A waveform 421 is obtained by dividing the frequency of the waveform 421 by two using a frequency divider 387.
Obtain 2°. Switches 329 and 330 to change the waveform 422
The waveform 422 is inverted by an inverter 334 and input to a terminal of the RAM 332. If the selector switches 329 and 330 are controlled to connect to the A side when the control signal of the terminal S is Low, and to connect to B@ when the control signal is High, the RAMs 331 and 33
2 can be used by switching between read and write in a seesaw pattern every two frames.

According to this embodiment, the transmission data string 100 shown in FIG.
can be demodulated, and as explained in FIG. 1, interference from the video signal can be reduced.

Note that depending on the initial state of the frequency divider such as the divider 390 when the power is turned on, if the waveform 412 becomes inverted or otherwise other than necessary for image interpretation, it may not operate normally; 9 sets etc. is possible.

FIG. 20 shows a specific example of the storage circuit 20 and timing recovery circuit 21 of the demodulation circuit that receives the transmission data string 109. Components with the same symbols as in FIG. 18 indicate the same functions. Further, FIG. 21 is an explanatory diagram of the operation of FIG. 20.

450.457, 458, 441, 450 are 2 frequency dividers,
451.452, 439° 440.444, 453 are latches, 455, 442, 445, 452 are shift registers, 454, 456, 443, 447.451 are inverters, 435.448 are NAND gates, 446 are Eo
ll gate and 449 are AND gates. 460 is the timing waveform for frame synchronization, 461 is the horizontal opening w4FF
4 timing waveform, 462 is the timing waveform for data synchronization, 463 is the received data string, 464 is the output data string of the delay device 17, 465 is the output data string of the subtractor 1st, 466
is the output data string of the shift register 452, 467 is the output waveform of the frequency divider 438, 468 is the output waveform of the frequency divider 441, 469 is the third stage output waveform of the shift register 442, and 470 is the output of the EOR gate 446. Waveforms, 471 is the first stage output waveform of the shift register 445, 472 is the second stage output waveform of the shift register 445, 473 is the output waveform of the NAND gate 448, 474 is the output waveform of the AND gate 449, 475 is the frequency divider by 2 Output waveform of 430, 476
is the output waveform of latch 476, 477 is NAND gate 4
35 output waveform, 478 output waveform of latch 432, 4
79 is the output waveform of the shift register 433, 480 is the initial state of the write address, 481 is the write address, 48
2 is the output waveform of the decoder 328, 485 is the latch 44
0 output waveform, 484 is the output waveform of 2 frequency divider 437, 4
85 is the output waveform of the latch 439, 486 is the counter 32
5, 487 is the output data string of latch 455, 488 is the output waveform of latch 444, 48
9 is the output waveform of the frequency divider 450 by two.

The received data string 46 is obtained from the data string 464 obtained by delaying the received data string 463 by one horizontal scanning period T by the delay device 17.
3 is subtracted by the subtracter 18, and a data string 465 of digital values is obtained by the clock recovery circuit 23 and code identification circuit 22. The data string 465 is shifted three times by the shift register 452 at the falling edge of the waveform 462, and the data string 465 is shifted three times by the shift register 452.
Get 66. In the data string 466, the 0 symbol is e+,
e2. The symbol X indicates necessary data other than es and f1, and the symbol X indicates unnecessary data. Divide waveform 461 by 2 J 441
The waveform 468 obtained by dividing the frequency by two is shifted three times by the shift register 442 at the falling edge of the waveform 462 to outperform the waveform 469. The waveform 462 is divided by 2 by the frequency divider 438.
Waveform 467 and waveform 469 obtained by frequency division are passed through BOR gate 446 to obtain waveform 470.

The waveform 468 is shifted twice by the shift register 442 at the falling edge of the waveform 462, the resulting waveform is shifted once by the shift register 445 at the rising edge of the waveform 462, and the waveform 471 is shifted three times, and the waveform 472 is obtained by shifting the waveform 468 three times. get. A waveform 475 is obtained by inverting the waveform 472 by an inverter 447 and the waveform 471 through a NAND gate 44B. Waveform 470 and waveform 475 are
Waveform 474 is obtained through ND gate 449. Waveform 46
A waveform 475 obtained by dividing 0 by 2 by a frequency divider 430 is latched by a latch 431 &C at the falling edge of the waveform 461 to obtain a waveform 476. Waveform 476 and Waveform 46
1 through a NAND gate 435.
The first falling edge delay 452 of 7 is preset to obtain waveform 478. Waveform 478 is shifted four times by shift register 433 at the falling edge of waveform 462 to obtain waveform 479. A write address 481 is generated by inputting waveform 474 as a clock signal and waveform 479 as an enable signal to counter 526. 4
80 is the initial state of the write address. Decoder 32
The waveform 482 obtained by decoding the write address rN-1J at 8 is latched at the falling edge of the waveform 474.
40 to obtain a waveform 483. If the waveform 485 is used as the clear signal for the counter 326, the counter 526 will be
A write address from ``0'' to ``N-1'' is generated. Data string 466 is written to RAM 5 by write address 481.
Write to 31.332. The waveform 462 is transferred to the inverter 45
6, the frequency is divided by 2 at the 2nd station a457, and waveform 4 is obtained.
Get 84.

Latch 4 waveform 483 at the falling edge of waveform 484
59 to obtain waveform 485. A read address 486 is generated by inputting waveform 484 as a clock signal to counter 325 and inputting waveform 485 as a clear signal. Read address 486 causes RAM 331.
The data read from 552 is latched at the falling edge of waveform 467 to obtain data string 487.

Latch 4 waveform 485 at the rising edge of waveform 462
A waveform 488 obtained as an inverted output is divided by two by a frequency divider 450 to obtain a waveform 489. The waveform 489 is input to the control terminal S of the selector switch 529.350 and the terminal of the RAM 552, and the waveform 489 is inverted by the inverter 334 and input to the terminal of the RAM 332. If the changeover switches 329 and 330 are controlled to connect to the KA side when the control signal of the terminal S is Low, and to the B side when it is High, the RAMs 331 and 332 can be connected to the KA side.
It can be used by switching between read and write in a see-saw pattern for each frame.

According to this embodiment, the transmission data string 109 shown in FIG. 14 can be demodulated, and as explained in FIG. 1, interference from the video signal can be reduced.

Figures 16, 18, and 20 are the memory circuits shown in Figure 1.
This is a detailed explanation of the timing reproducing circuit Cl1l, in which a RAM is used in the memory circuit to select necessary data and expand the time axis.

Furthermore, in the embodiments in which a RAM is used as a storage circuit as shown in FIGS. 16, 18, and 20, interleaving of a transmission data string can be solved using a RAM.

In FIG. 22, 500K shows an example of a normal data string before interleaving and 501 shows an example of a data string after interleaving. In the 22nd factor, the numbers in the box indicate the order of data strings before interleaving, and it is assumed that interleaving is completed with 12 data.

Before showing a specific example of a circuit for canceling interjeep, first, the detailed circuit of the write address counter 525, read address counter 326, and switches 529, 350 shown in FIGS. 16, 18, and 20 is shown in FIG. 23. show.

Further, FIGS. 24, 25, and 26 are explanations of the operation of FIG. 25.

In FIG. 23, 525 is the counter 518
No. 5 input terminal, 526 is a clock signal input terminal for counters 517 and 518, 527 is an enable signal input terminal for counter 517, 528 is a clear signal input terminal for power wantter 516, 529 is a clock signal input terminal for counters 515 and 516, 515, 516, 517, 518 are counters, 519° 520 are switches, 507, 509, 5
11.515 is an AND gate, 508,510.512
1514 is an inverter, and 505.50tS is a latch.

530 is the input clock waveform of counters 517 and 518;
551 is the clear input waveform of the counter 517, 532 is the Q1 output waveform of the counter 517, and 533 is the counter 517
554 is the output waveform of the AND gate 511, 535 is the output waveform of the latch 506, 536 is the Q1 output waveform of the counter 518, 537 is the Q of the counter 518
2 output waveforms, 538 is a write address generated by counters 517 and 518, and 539 is an input data string.

The input clock 530 is divided by the write address counter 517 to obtain a Q1 output waveform 532 and a Q2 output waveform 535. Waveform 534 is obtained by passing the inverted modification of waveform 5520 and waveform 555 through AND gate 511. Waveform 534 is latched by latch 506 at the falling edge of waveform 530 to obtain waveform 535. Waveform 535 is converted to counter 518
The inverted waveform of the waveform 535 and the waveform 531 are passed through the AND gate 513 to be cleared No. 41 of the counter 517. If the waveform 530 is inputted to the counter 518 as a clock signal and the waveform 531 is inputted as a clear signal, it will outperform the modified Q1 output waveform 536 and the Q2 output waveform 537. If waveform 552 is used as an LSD and waveforms 555, 556, and 557 are used as write address signals in order, a write address shown at 558 is generated. The alphanumeric characters in 538 indicate the address. For example, if it is AO, it is address 0. Read address counter 515, 5
Generating a read address using 16K is performed in exactly the same nine lines, so a description thereof will be omitted here. FIG. 26 shows the state of read/write when using R and AM of the address map shown in FIG. 25 as a memory circuit. The alphanumeric characters in the box in Figure 25 indicate the address. Write address 5
58, the input data string 539 is written by &c5 data in the vertical direction, and reading is performed in exactly the same manner.

Next, FIG. 27 shows a specific example of solving the interjeep shown in FIG. 22 using KR and AM. 28 and 29 are explanatory diagrams of FIG. 27.

In FIG. 27, the same reference numerals as in FIG. 23 indicate the same functions.

540 is the input clock waveform of the counters 515 and 516;
541 is the clear input waveform of the counter 516, 542 is the Q1 output waveform of the counter 515, and 543 is the counter 515
544 is the output waveform of the AND gate 507, 545 is the output waveform of the latch 505, 546 is the Q1 output number form of the counter 516, 547 is the Q of the cuxter 516
It is a 2-output him type.

The difference between FIG. 23 and FIG. 27 is that in FIG. 27, the inverter 508 is black < the decoded value of AND gate 507 is 1-3
” and the read address counters 515, 51
6 and the switches 519 and 520 are connected in a reverse trap.

The procedure for generating a write address is the same as that shown in FIGS. 23 and 24. A read address is generated as follows. Divide the input clock 540 by the read address counter 515 and output Q1? J[4-542, get Q2 output hexagonal 543. AND waveform 542 and waveform 543
Output waveform 544 is passed through gate 507 .

Latch 5 waveform 544 at the falling edge of waveform 540.
It latches by 05 and goes through waveform 545. waveform 545
is the enable signal for the next stage force controller 516, and the waveform 54 is
The signal obtained by passing the inverted signal of 5 and the waveform 541 through the AND gate 509 is used as the clear signal of the counter 515. In addition, the waveform 540 is applied to the power controller 516 as a clock signal.
If the waveform 541 is input as a clear signal, the Q1 output waveform 546 of the counter 516 and the Qz output waveform 547
get. Forward Kff type 547 with waveform 546 as LSB,
If waveform 542 and waveform 543 are used as read address signals, read address 548 is generated. If the write address is set to 538 and the read address is set to 548, the data string stored in the vertical direction of the RAMK can be read out in the horizontal direction, as shown in FIG. The data string read by this operation becomes the original data string 549 in FIG. 28 and can be deinterleaved.

Therefore, according to the trap of this embodiment, FIGS. 6, 11, and 14
The transmission signal shown in the figure can be demodulated, and interleaving is also effective.

An embodiment of the pond of the present invention is shown in FIG. 190 is a filter, 191 is a frequency conversion circuit, and the same symbols as in FIG. 1 indicate the same functions. The difference from FIG. 1 is that a filter 190 and a frequency conversion circuit 191 are provided in order to lower the frequency for demodulating the digitally encoded and multiplexed audio signal than the frequency for demodulating the video signal.

According to this embodiment, the intermediate frequency of the output of the frequency conversion circuit 3 (58, 75 MH for Japanese terrestrial television)
The video signal is demodulated using the frequency conversion circuit 191 (often commonly used), and the digitally encoded and transmitted audio signal is demodulated using a lower intermediate frequency (for example, about 5Mk4z) output from the frequency conversion circuit 191. Therefore, as the frequency becomes lower, position errors caused by traps such as circuit delay time of the carrier wave reproduced by the carrier wave recovery circuit 16 used in the synchronous detection circuit 15 are reduced, and the digitally encoded and transmitted audio signal can be stably demodulated. There is an effect that can be done.

A further embodiment of the pond according to the present invention is shown in FIG. Components with the same reference numerals as in FIGS. 1 and 30 indicate the same functions. W is a frequency conversion circuit, 195 is a mixing circuit, 194 is a voltage-controlled local oscillator, 195 is a reference signal generator, 196 is a low-pass filter, and the frequency conversion circuit 191 in FIG. 19 is connected to the mixing circuit 193 and voltage control. It consists of a local oscillator 194 of the form.

The difference from FIG. 30 is that in FIG.
6, the digitally encoded audio signal is detected by the synchronous detection circuit 15 in synchronization with the digitally encoded audio signal that is orthogonally modulated with the video signal of the carrier wave reproduced in FIG. Using the fact that the modulation by the signal and the modulation by the video signal are orthogonal, the phase difference between the reference signal generator 195 and the intermediate frequency signal containing the carrier acid is detected by the synchronous detection circuit 15 and the low-pass filter 196. death,
By feeding back to the voltage-controlled local oscillator 194, the intermediate frequency carrier wave is synchronized with the output of the reference signal generator, and the output of the synchronous detection circuit 15 is used as a detected output.

According to this embodiment, since it is a negative feedback loop in which the number of intermediate legs a for demodulation matches the frequency of the reference signal generator 195,
The frequency shift of the band pass filter 140 due to K, such as the frequency drift of the frequency conversion circuit 3, and the demodulation frequency drift are small (there is an effect that demodulation can be performed more stably than the embodiment shown in FIG. 19).

Still another embodiment of the present invention is shown in FIG. Components with the same symbols as in FIG. 31 indicate the same functions. 197 is a temple hold circuit. The difference from FIG. 31 is that the sample/hold circuit 197 enters the loop of the carrier wave recovery circuit, and the timing recovery circuit 21 controls the sample/hold circuit wr197.

According to this embodiment, when *@ of the video signal 1g becomes large, such as the horizontal synchronization pulse period of the video signal 5 of the output of the synchronization detection circuit 15, the system is stabilized by holding the period. .

Yet another embodiment of the invention is shown in FIG. Components with the same symbols as in FIG. 37 indicate the same functions. 202 is a synchronous detection circuit, and 203 is a phase shifter. The difference from FIG. 23 is that the same detection circuit 202 is used for the output of the band-pass filter 4, and the phase shifter 205 is used for the output signal of the reference signal generator 195! -Using a video signal that is synchronously detected using a phase-shifted signal. As a result, the synchronization signal detection circuit 2 of the input signal
The time to 00 and the time to synchronous detection circuit 15 match, and the time for delay circuit 201 can be reduced.

According to this embodiment, the time required by the delay circuit 2010 can be reduced, thereby increasing the effect of enabling more stable reception.

Yet another embodiment of the invention is shown in FIG. Components with the same symbols as in FIG. 31 indicate the same functions. 210 is the control ID
This is a code reproducing circuit. The difference from FIG. 31 is that the received control signal is reproduced from the output of the code identification circuit 22, and the storage circuit 20 is controlled via the timing reproduction circuit 21 in accordance with the control signal.

According to this embodiment, since the timing is generated based on the control signal, there is an effect that more stable reception and reproduction can be performed with 0J performance.

FIG. 35 shows an embodiment of a transmitter that transmits an additional control signal. As a control signal, the number of increased or decreased data numbers, a signal indicating the horizontal scanning period, a signal indicating whether the first multiplexed signal of the horizontal scanning period is the same signal in reverse phase as the multiplexed signal of the adjacent scanning period above or below, or vertical scanning. Signal indicating position relative to period, odd/even field discrimination signal, odd/even field discrimination signal
An even number frame discrimination signal may be considered. 220 is a timing generation circuit, 221 is a control signal generation circuit, 222 is a changeover switch, and the reference numerals 4 and 4 in FIG. 2 indicate the same functions. Digital signal processing circuit 43A and processing circuit 43
The output of B and the output of the control signal generation circuit 221 are time-division multiplexed with the control signal and data from the digital signal processing circuit by switching the changeover switch 222 at the timing of the timing generation circuit 220. Note that only the period of control signals etc. (
Since data cannot be transmitted only during the period when the changeover switch 222 is in contact with the control signal generation circuit 221 side, the digital signal processing circuit 45A or the processing circuit as
Stop the output of k3. In addition, in order to prevent the data during the stop period from being discontinuous, the digital signal processing circuit 45A or the processing circuit 438 compresses the time axis of the data in advance, so that the intermittent data with an interval of time rIJIVc for control signals, etc. do. The resulting multi-iLig
An example of the number is shown in Figure 36. 223 is a vertical synchronization signal, 22
4 is a horizontal synchronizing signal, 225 is a multiplex signal, and 226 is a temporal expansion signal of the multiplex signal. In this example, it is shown in conjunction with a television horizontal assistance signal. Horizontal opening, period 1g
The next one of the equalization pulse periods after the vertical synchronization period of No. 224
This is an example in which a 16-bit synchronization signal, a 32-bit control signal, and 48 bits of data (denoted by C) are added to the next horizontal scanning period in reverse phase (indicated by C) during the horizontal scanning period. If this control signal period is set twice every two vertical periods, then in the case of the current Japanese TV program, one horizontal scanning period M out of 525 horizontal scanning periods is the control signal period, so the output of the processing circuit 45B is The data can be time-axis compressed at a ratio of 525/525.

According to the present embodiment, the polarity of the multiplexed signal, the horizontal scanning period number, the field number, the frame number, the increase/decrease in the transmission capacity of the multiplexed signal in the horizontal scanning period, and the increase/decrease Since this can be done using a control signal such as a horizontal scanning period number, it is possible to easily and stably operate the signal processing of the receiver.

Yet another embodiment of the invention is shown in FIG. Components with the same symbols as in FIG. 20 indicate the same functions. 270 is an interpolation control circuit. The difference from Fig. 31 is interpolation 1W11.
As explained in FIG. 1, in the case of highly correlated video images in adjacent horizontal scanning periods, the interference from the video can be reduced by 70% by subtracting with the subtractor 18. (Image 1 with adjacent horizontal scanning periods such as the horizon)
1 (images with many K differences), it cannot be reduced by 7 times, and the data in the horizontal scanning period is likely to be erroneous. Therefore, when the receiver begins to receive many errors due to transmission, the digital signal processing circuit 24 starts from error correction to interpolation operation.
Furthermore, the interpolation control circuit 270 does not use the data in the horizontal scanning period with many errors for error interpolation, but performs interpolation from data in another horizontal scanning period.

In this embodiment, interpolation is performed from data of another horizontal scanning period with fewer errors, so interpolation can be performed effectively and stable 1g reproduction can be obtained.

〔Effect of the invention〕

According to the present invention, the same multiplexed signal is transmitted to 21! Since the signal transmitted visually can be subtracted and reproduced, it has the effect of reducing interference from video 1g, such as ghosts.

FIG. 38 shows a diagram illustrating the present invention in detail. The horizontal axis shows the ghost level (the one on the right is very low), and the vertical axis shows the digital transmission pit error rate.
The receiving circuit shown in the figure, the transmitting circuit shown in Fig. 2, the multiplexed signal arrangement shown in Fig. 12, the video signal being a color par, and the ghost delay time being a delay time orthogonal to the video. In addition, white noise was added during the measurement to generate bit errors. The carrier-to-noise ratio of the orthogonal modulation component at that time is expressed as C/N.

500 indicates the case where the subtraction of the present invention is not used, and 301 indicates the case where the subtraction of the present invention is used. Same bit error rate 1
When compared at 0, the subtraction of the present invention has the same amount of ghosts by about 15 dB, indicating the effect of reducing image ghosts by that much. In addition, although the C/N of 301 using the subtraction of the present invention is 3 dB lower (there is more noise), the error rate is the same as that of -50 dB of ghost, which is due to the subtraction of the backward output of the transmission signal. Although the amplitude is doubled, the noise is only four times as large, showing an improvement of 5 dBOC/N.

[Brief explanation of the drawing]

Figure 1 is a diagram of an embodiment of the present invention, Figure 2 is a diagram of a specific example of the signal generator of the present invention, Figure 3 is a spectrum diagram for explaining the present invention, and Figure 4 is an explanation of the present invention. Vector diagram for, No. 51ii! 'l is an example diagram of the main part of the signal generation of the present invention, the 6th factor is a waveform diagram for the present invention, Figure 7 is the screen pattern @ pseudo diagram of the rice signal of the present invention, Figure 8 is a vector diagram for explaining the present invention, the 9th factor is a waveform diagram for explaining the present invention, the 10th factor is a specific example diagram of a pond that is the main part of signal generation of the present invention, and FIG. 11 is a diagram of the present invention FIG. 12 is a screen pattern diagram of the transmission signal of this research, FIG. 13 is another specific example of the main part of No. 4g generation of the present invention, and FIG. 111g14 is a waveform diagram for explaining. A waveform diagram for explaining the present invention, FIG. 15 is #1 of still another transmission damage signal of the present invention.
Figure 16 is a concrete example of the main part of the present invention, Figure 17 is an explanatory diagram of the operation of the main part of the present invention, and Figure 18 is a concrete example of the pond of the main part of the present invention. FIG. 19 is another explanatory diagram of the operation of the main part of the present invention, FIG. 20 is a diagram of still another specific example of the main part of the present invention, and FIG. 21 is an explanatory diagram of further operation of the main part of the present invention. Fig. 22 is a diagram of a rice transmission signal pattern of the present invention, Fig. 23 is a diagram of still another specific example of the main part of the present invention, Fig. 24 is a diagram illustrating still another operation of the main part of the present invention, and the 25th factor is An explanatory diagram of the operation of oil in the main part of the present invention,
FIG. 26 is an explanatory diagram of another operation of the main part of the present invention, FIG. 27 is a diagram of still another specific example of the main part of the present invention, and FIG.
29 is an explanatory diagram of still another operation of the main part of the present invention, FIG. 30 is a diagram of still another embodiment of the present invention, and FIG. FIG. 32 is an embodiment of a further pond of the present invention, FIG. 33 is an embodiment of a further pond of the present invention, and FIG. 34 is still another embodiment of the present invention. 35 is a diagram of another specific example of the signal generator of the present invention, FIG. 36 is a waveform diagram of another transmission signal of the present invention, tJI, and FIG. 57 is a diagram of an embodiment of the present invention, FIG. 58 is an explanatory diagram of the effect of the present invention. 15... Synchronous horizontal circuit, 17... Delay circuit, 18.
...Subtractor, 20...Storage circuit, 1914 Shimokawa frequency ridge conversion circuit, 20°...Synchronization signal detection circuit. 312I Compilation 4 @ High 5 Figure 7 Round 8 Ru (0-) (b) Ya 5tn (1) C Nanase 9 Leap (fl) Ar1 (b) Hayabusa IO Figure Challenge 12 Figure 13 Figure 22 500 1 2 3 4-5 6 7 8 9 10
11 /2501 1 5'? 2 6 10
3 7 11 +8 12OζC'JI? ) ÷ Me bite's > of 勺 n 庺's of 勺 rr) (n of
Figure 826 Figure $29 Figure

Claims (1)

[Claims] 1. A first carrier wave whose amplitude is modulated by a first signal;
Receiving a multiplexed transmission signal transmitted by combining a second carrier wave having a quadrature phase relationship with the first carrier wave, which is amplitude-modulated by a second signal that is repeatedly sent multiple times every certain period. a carrier wave regeneration circuit that regenerates the second carrier wave from the multiplex transmission signal; a synchronous detection circuit that synchronously detects the multiplex transmission signal using an output of the carrier wave regeneration circuit and demodulates the second signal; With respect to the second signal which is the output of the synchronous detection circuit,
an arithmetic processing circuit that delays the second signal by passing it through a delay circuit that delays the repetition period, and then performs processing such as subtraction between the second signal and the signal before the delay; and from the arithmetic processing circuit. 1. A multiplex transmission signal reproducing device comprising: a storage circuit that stores the output of and performs time axis expansion thereof. 2. In the multiplex transmission signal reproducing device according to claim 1, the storage circuit is comprised of a dual-purpose storage circuit having the functions of both a time axis expansion circuit and a deinterleave processing circuit for error correction. A multiplex transmission signal reproducing device characterized by: