JPH01172779A - Test waveform generator in ic testing apparatus - Google Patents

Abstract

PURPOSE:To simply generate a complicated test waveform, by generating data for forming the test waveform in a data generating means corresponding to the characteristic of an IC to be tested. CONSTITUTION:A waveform generating means forms a test waveform on the basis of the data and clock pulse respectively supplied from a data generating means and a clock pulse control means. For example, the data generating means is a memory and data for forming the test waveform corresponding to an IC to be tested is read from said memory to be given to the clock pulse control means and the waveform generating means. On the basis of this data, the clock pulse from the clock pulse generating means is masked for an arbitrary tie by the clock pulse control means. For example, the waveform generating means sets the level of the waveform generated on the basis of the data supplied from the data generating means and changes over said level on the basis of the clock pulse supplied from the clock pulse control means to generate a waveform.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC testing device capable of generating a plurality of types of test waveforms, and particularly to an arrangement that can increase the types of test waveforms that can be generated.

[Prior Art] Examples of test waveform generation circuits in IC test equipment include:
Conventionally, as shown in FIG. 3, test waveform creation data is supplied from a data memory 102 via a test waveform creation data bus SBD, and each clock pulse X is supplied from a clock generation circuit 104.

Based on Y and Z, the test waveform P was generated in the test waveform generation circuit 103.

In FIG. 3, a control unit 101 operates and manages the entire IC testing apparatus. A control signal is given from the control unit 101 to the data memory 102 via the bus DB,
Test waveform creation data is read from the data memory 102 in response to this control signal. The data memory 102 is
This is a read-only memory that stores various test waveform creation data. The test waveform creation data read from the data memory 102 is transferred to the test waveform creation data bus S.
The signal is applied to the test waveform generation circuit 103 via the BD. The test waveform generation circuit 103 sets the voltage H at the high level and the voltage at the low level of the test waveform P based on the test waveform creation data given from the data memory 102, and sets the voltage H at the high level and the voltage at the low level of the test waveform P, and generates a clock pulse X given from the clock generation circuit 104. ,
The test waveform P is generated by switching between the voltages H and L in synchronization with Y and Z. In a normal IC test, the test waveform P output from the test waveform generation circuit 103 is applied to an IC under test (not shown) to determine 1itq.

The test waveform generation data given to the test waveform generation circuit 103 is level data for setting the high level voltage H and low level voltage of the test waveform P to be applied to the IC under test. The clock pulses x, y, and z are pulses having the same predetermined frequency and having one phase difference (see FIG. 4).

When testing a desired IC, the control unit 101 presets level data for setting the high level voltage H and low level voltage of the test waveform P according to the characteristics of the IC under test, and also sets each level data in advance. clock pulse x, y
, z and their respective phase differences are initialized. Control unit 101 sends a control signal to data memory 102 according to this initial setting data. Based on the control signal, test waveform generation data is read out from the data memory 102, and the test waveform generation circuit 1
Given to 03. The test waveform generation circuit 103 sets the high level voltage H and low level voltage of the test waveform P to be generated according to the given test waveform creation data,
Each clock pulse X, Y given from the clock generation circuit 104.

The test waveform P is generated by switching between the voltages H and L in synchronization with Z. For example, in FIG. 4, it is assumed that the period of each clock pulse x, y, z is 3Qmsec. The Y clock is delayed by 10m5ec from the X clock, and the Z clock is delayed by 25m5ec from the X clock.
It is a delayed phase. Furthermore, assuming that the high level voltage H of the test waveform P is 5V and the low level voltage L is OV,
The test waveform P generated in the test waveform generation circuit 103 is as shown in FIG.

The high level voltage H=5V and the low level voltage L=OV of the test waveform P are switched by the first X clock pulse. At 10 m5 ec, a later Y clock pulse causes the high level voltage H and low level voltage of the test waveform P to switch to a low level, opposite to the level switched by the first X clock pulse. Next, 25m5ec against X clock.

Due to the shifted Z clock, the test waveform P is switched between a high level voltage H and a low level voltage. In this way, in the test waveform generation circuit 103, the level of the test waveform P is set based on the test waveform creation data, and the high level voltage H and the low level voltage are switched in synchronization with clock pulses of the same frequency and different phases. By this, the test waveform P
Create and output. At this time, three types of test waveforms P can be applied to the IC under test by shifting the phases of the clock pulses x, y, and z at appropriate intervals for each cycle in which the IC is tested.

[Problems to be Solved by the Invention] In recent years, there has been a trend toward higher density integration of ICs, and there is a problem in that the conventional test waveform creation method described above cannot cope with the diversification of test waveforms. Ta. Since the test waveform was created by switching the high level voltage H and low level voltage set by the test waveform creation data every test cycle using multiple clock pulses, only three types of waveforms were obtained that corresponded to the types of clock pulses. I couldn't do that. Therefore, there was a problem in that it was not possible to cope with the increasing complexity of test waveforms.

This invention was made in view of the above points, and is an IC that can easily generate complex test waveforms.
The present invention provides a test waveform generator for a test device.

[Means for solving the problem] A test waveform generator in an IC tester according to the present invention is a test waveform generator that generates a test waveform to be applied to an IC under test in the IC tester, a clock generating means for generating a plurality of clock pulses having different predetermined phase relationships; and a clock generating means for generating a plurality of clock pulses having different predetermined phase relationships; A clock pulse control means for masking a pulse at an arbitrary time; and a waveform generation means for creating the test waveform based on the data and the clock pulse supplied from the data generation means and the clock pulse control means. It is something that

[Operation] The data generating means generates data for creating a test waveform according to the characteristics of the IC to be tested.

The clock generating means generates a plurality of clock pulses having different predetermined phase relationships. The clock pulse control means masks any clock pulse at any time based on the data generated by the data generation means. The waveform generation means creates a test waveform based on the data and clock pulses supplied from the data generation means and the clock pulse control means. For example, the data generation means is a memory, and data for creating a test waveform corresponding to the IC under test is read from the memory and provided to the clock pulse control means and the waveform generation means. Based on the data, the clock pulse control means masks (that is, suppresses) any clock pulse from the clock generation means for any desired time. The waveform generating means sets the level of the generated waveform based on, for example, data supplied from the data generating means, and generates the waveform by switching the level based on the clock pulse supplied from the clock pulse controlling means.

[Example 7] Hereinafter, an example of a test waveform generator in an IC test apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a test wave) b generator in an IC testing apparatus according to the present invention. Note that only the parts directly related to the present invention are shown. The control unit 11 operates, manages, and controls the entire IC testing device. The control unit 11 stores data instructing whether or not masking of each clock pulse x, y, and z is necessary in each mask register 13 to 15.
It also provides data for controlling the data memory 12 to the data memory 12 via the bus DB. When masking the clock pulse X, the control unit 11 applies 171 I+ to the mask register 13, and
3 stores this in memory and gives it to Nantes Gate 16. Similarly, when masking the clock pulse Y, the control unit 1
1 gives "1" to the mask register 14, stores this in the register 14, and gives it to the NAND game 17. Further, when masking the clock pulse Z, the control unit 11 gives “1” to the mask register 15,
This is stored and held in the register 15, and the Nantes gate 18
give to

The data memory 12 is a read-only memory that stores data for creating various test waveforms. The test waveform creation data read from the data memory 12 is given to the test waveform generation circuit 22 via the test waveform creation data bus SDR, and is also applied to each of the Nantes gates 16 to 18.
given to.

Data for setting the high level voltage H and low level voltage of the test waveform TP is supplied from the data memory 12 to the test waveform generation circuit 22. From the data memory 12, each clock pulse X, Y,
Mask enable signals MEX, MEY, and MEZ for controlling the Z masking timing are provided, respectively.

The generation timing of the mask enable signals MEX, MEY, and MEZ can be arbitrarily set in the control section 11 according to the test waveform to be created.

In the Nant gate 1G, both the mask enable signal ME applied to one input from the data memory 12 and the output of the mask register 13 applied to the other input are "1".
, an active 0'' is applied to one input of the AND gate 19 as a mask signal MX for masking the clock pulse When the enable signal MEY and the output of the mask register 14 applied to the other input are both 1'', an active 110 It is applied to one input of the AND gate 20 as a mask signal MY for masking the clock pulse Y. . Furthermore, when the mask enable signal MEZ applied to one input from the data memory 12 and the output of the mask register 15 applied to the other input are both "1", the Nant gate 18 outputs a signal for masking the clock pulse Z. An active "0" is applied to one input of the AND gate 21 as the mask signal MZ. In addition,
Each mask enable signal MEX.

MEY and MEZ are the corresponding clock pulses x,
This is a timing signal for suppressing (that is, masking) y and z, and this signal causes the Nantes gate 16 to
An active (that is, valid) "0" is given to each AND gate 19 to 21 as mask signals MX, MY, and MZ from the respective outputs of the AND gates 19 to 18. Clock pulse X is applied from 23, and when mask signal MX is "11", clock pulse X is selected and applied to test waveform generation circuit 22.

Similarly, the other input of the AND gate 20 is given a clock pulse Y from the clock generation circuit 23.
When the mask signal MY is "1'", the clock pulse Y is selected and applied to the test waveform generation circuit 22. Further, the clock pulse Z is applied from the clock generation circuit 23 to the other input of the AND gate 21, and when the mask signal MZ is 1'', the clock pulse Z is selected and applied to the test waveform generation circuit 22.

The test waveform generation circuit 22 sets a high level voltage H and a low level voltage H of the test waveform TP based on the test waveform creation data supplied from the data memory 12, and supplies the high level voltage H and low level voltage H from each of the ant games 1-19 to 21, respectively. The test waveform TP is created by alternately switching between the voltage H and the voltage R in synchronization with clock pulses x, y, and z.

The clock generation circuit 23 generates clock pulses x, y, and z of the same frequency and different phases. Each clock pulse X, Y, generated by the clock generation circuit 23
The frequency and phase of Z can be arbitrarily set by the control unit 11 according to the IC to be tested.

Next, the operation of each part in the above configuration will be explained. First, under the control of the control unit 11, data for creating a desired test waveform TP according to the IC under test is stored in the data memory 1.
2, and sets respective data instructing whether or not masking of clock pulses , Z is set to, for example, 30 m5ec. Based on the test waveform creation data read from the data memory 12, the test waveform generation circuit 22 sets the level of the test waveform to be created to, for example, high level voltage H-=5■ and low level voltage L=OV. do. Also.

Based on the test waveform creation data read from the data memory 12, each mask enable signal MEX, MEY is applied to the Nant gates 16-18.

The timing of MEZ is, for example, as shown in the time chart shown in FIG. The mask enable signal MEZ is applied 3m5ec after the third clock pulse Z until 18m5ec after the third clock pulse Y.

It is set to be active until 3 m5ec after the fourth clock pulse Z from the end.

In this case, all clock pulses x, y, z are masked in their respective predetermined periods.

Data instructing masking is given to all the mask registers 13-15 from the control unit 11, and these data are stored and held in the respective mask registers 13-15.

At the time of the first clock pulse
-19 allows the clock pulse X to pass through without masking, and supplies the clock pulse X to the test waveform generation circuit 22. In synchronization with this clock pulse X, the test waveform generation circuit 22 switches the level of the generated waveform from the low level voltage L=OV to the high level voltage H=5V. Next, at the time of the first clock pulse Y, which is shifted by 30 m5ec with respect to the clock pulse
Therefore, the AND gate 20 masks (suppresses) the clock pulse X. In this case, since no clock pulse is supplied to the test waveform generation circuit 22, the level of the test waveform to be generated does not change. At the time of the first clock pulse Z, the mask enable signal MEZ is 1.
10", the mask signal MZ output from the Nant gate 18 becomes "1". Therefore, the AND gate 19 passes the clock pulse Z without masking it and supplies the clock pulse X to the test waveform generation circuit 22. In synchronization with this clock pulse Z, the test waveform generation circuit 22 changes the level of the waveform to be created to a high level voltage H=
Switch from 5V to low level voltage L=OV.

Similarly, each mask enable signal MEX, MEY.

When each MEZ is in the “0” state, the mask signal M output from the corresponding Nantes gates 16 to 18.
X, MY, MZ become "1", therefore, each clock pulse x, y, z is connected to the corresponding AND gate 19-21, respectively.
The test waveform generation circuit 22 is passed through without being masked by
is supplied to

In the test waveform generation circuit 22, in synchronization with the supplied clock pulses
5V and 5V alternately.

Additionally, each mask enable signal MEX, MEY.

When the MEZ signal is in the state of '1', the mask signals MX, MY, M output from the respective Nantes gates 16 to 18
Z becomes active 0'' and each clock pulse x, y, z is therefore masked respectively by the respective AND gates 19-21. Any clock pulse X, Y
, Z are masked, the test waveform generating circuit 22 does not switch between the low level voltage and the high level voltage H of the test waveform to be created, but remains at the level switched by the previous clock pulse.

In this way, the low-level voltage and high-level voltage H of the waveform to be created according to the IC under test are alternately switched in synchronization with the plurality of supplied clock pulses, and any clock pulse can be applied at any time. Because masking can be performed with

In this example, the levels of the test waveform TP are set to high level voltage H = 5V and low level voltage L = OV, but any other suitable level may be used as long as it is a level that corresponds to the IC under test. Good too.

Also, in this example, each clock pulse X.

Although a Nant gate and an AND gate are used as circuits for masking control of Y and Z, other logic circuits may be used as long as the circuit configuration can achieve the object of the present invention.

In addition, the time chart in FIG. 2 shown in this example is as follows:
This does not limit the characteristics of the test waveform generator according to the present invention.

[Effects of the Invention] As described above, according to the test waveform generator in the IC test apparatus according to the present invention, the level of the test waveform to be applied to the IC under test can be arbitrarily set, and the level of the test waveform to be applied to the IC under test can be set at an arbitrary timing. Since the test waveform can be switched between low level voltage and high level voltage H,
Even complex test waveforms can be created easily. Therefore,
It has various excellent effects, such as improving the efficiency of IC testing work and improving test accuracy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a test waveform generator in an IC testing device according to the present invention, FIG. 2 is an example of a timing chart of various signals in the same embodiment, and FIG. 3 is a conventional IC testing device. FIG. 4 is a block diagram showing an example of a test waveform generator in the conventional example, and FIG. 4 is an example of a timing chart of various signals of the conventional example. 11...Control unit, 12...Data memory, 13-15
. . . Mask register, 16 to 18 . . . Nant gate, 19 to 2 digits . Applicant Hitachi Electronics Engineering Co., Ltd. Agent
Patent Attorney Yoshi Iizuka

Claims (3)

[Claims] (1) A test waveform generator that generates a test waveform to be applied to an IC under test in an IC test device, which includes a data generation means for generating data for creating the test waveform, and a predetermined different phase. clock generation means for generating a plurality of related clock pulses; clock pulse control means for masking any one of the clock pulses at an arbitrary time based on the data generated from the data generation means; 1. A test waveform generation device for an IC test apparatus, comprising: waveform generation means for creating the test waveform based on the data and the clock pulse supplied from the clock pulse control means. (2) The IC testing apparatus according to claim 1, wherein the data generating means generates data for controlling the mask timing of each clock pulse and level data for setting the level of the test waveform. Test waveform generator. (3) The waveform generation means is configured to adjust the level of the test waveform supplied from the data generation means to each clock pulse supplied from the clock pulse control means in synchronization with each clock pulse supplied from the clock pulse control means. 2. A test waveform generator in an IC tester according to claim 1, which switches in synchronization with a pulse.