JPH01177612U - - Google Patents
Info
- Publication number
- JPH01177612U JPH01177612U JP1988073566U JP7356688U JPH01177612U JP H01177612 U JPH01177612 U JP H01177612U JP 1988073566 U JP1988073566 U JP 1988073566U JP 7356688 U JP7356688 U JP 7356688U JP H01177612 U JPH01177612 U JP H01177612U
- Authority
- JP
- Japan
- Prior art keywords
- resistance element
- logic circuit
- differential logic
- inverting input
- input side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Pulse Circuits (AREA)
Description
第１図はこの考案の実施例を示す接続図、第２
図はその動作タイムチヤート、第３図はこの考案
の他の実施例を示す接続図、第４図は第３図の等
価回路図、第５図は第３図の動作タイムチヤート
、第６図は従来の可変遅延回路を示す図、第７図
はその動作タイムチヤートである。
Figure 1 is a connection diagram showing an embodiment of this invention, Figure 2
3 is a connection diagram showing another embodiment of this invention. FIG. 4 is an equivalent circuit diagram of FIG. 3. FIG. 5 is an operation time chart of FIG. 3. FIG. 6 1 is a diagram showing a conventional variable delay circuit, and FIG. 7 is an operation time chart thereof.
Claims (1)
第１抵抗素子を通じて接続され、 第２入力端子が上記差動論理回路の反転入力側
に第２抵抗素子を通じて接続され、 上記差動論理回路の非反転出力側が第３抵抗素
子を通じて非反転入力側に接続され、 上記差動論理回路の反転出力側が第４抵抗素子
を通じて反転入力側に接続され、 上記第１抵抗素子、第２抵抗素子、第３抵抗素
子及び第４抵抗素子の少くとも一つは可変抵抗素
子とされている可変遅延回路。[Claims for Utility Model Registration] A first input terminal is connected to the non-inverting input side of the differential logic circuit through a first resistance element, and a second input terminal is connected to the inverting input side of the differential logic circuit through a second resistance element. The non-inverting output side of the differential logic circuit is connected to the non-inverting input side through a third resistance element, the inverting output side of the differential logic circuit is connected to the inverting input side through a fourth resistance element, A variable delay circuit in which at least one of a first resistance element, a second resistance element, a third resistance element, and a fourth resistance element is a variable resistance element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988073566U JPH01177612U (en) | 1988-06-01 | 1988-06-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988073566U JPH01177612U (en) | 1988-06-01 | 1988-06-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01177612U true JPH01177612U (en) | 1989-12-19 |
Family
ID=31298703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988073566U Pending JPH01177612U (en) | 1988-06-01 | 1988-06-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01177612U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH098616A (en) * | 1995-06-19 | 1997-01-10 | Nec Corp | Variable delay circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5928718A (en) * | 1982-08-10 | 1984-02-15 | Fuji Electric Corp Res & Dev Ltd | Delay circuit |
| JPS6054515A (en) * | 1983-09-05 | 1985-03-29 | Hitachi Ltd | Delay circuit |
-
1988
- 1988-06-01 JP JP1988073566U patent/JPH01177612U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5928718A (en) * | 1982-08-10 | 1984-02-15 | Fuji Electric Corp Res & Dev Ltd | Delay circuit |
| JPS6054515A (en) * | 1983-09-05 | 1985-03-29 | Hitachi Ltd | Delay circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH098616A (en) * | 1995-06-19 | 1997-01-10 | Nec Corp | Variable delay circuit |
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