JPH01177635A - System for controlling wait - Google Patents

Abstract

PURPOSE:To execute an apparent processor wait in a reference clock unit in which a period is faster than a system clock, and to efficiently operate a processor by controlling the system clock given to the processor by means of the timing of a reference clock. CONSTITUTION:When a wait instructing signal WAIT is inputted, the state of the processor (equal to a system clock period) is counted, and when a prescribed number T2 and a 2-state number of T3 set beforehand are attained, a resetting pulse is generated. Thereafter, the resetting pulse is completed in response to the terminating timing of a wait instructing input, a frequency- divider 2 starts the frequency-dividing action of the reference clock again synchronizing to the reference clock at such a time, and the generation of the system clock is resumed. Consequently, in the processor state T3, for example, a wait TW for the 1 period of the reference clock is applied, and the action cycle of the processor can be extended in appearance. Thus, a throughput can be improved.

Description

TECHNICAL FIELD The present invention relates to a wait control method, and more particularly to a wait control method for realizing a wait state by extending the operating cycle time of a processor.

BACKGROUND OF THE INVENTION Usually, in order to secure the access time required for memory and the I10 controller, a so-called wait control function is added to a processor to extend the memory read cycle and Ilo read/write cycle. It is common for this way 1 to control function to add an access cycle by giving a wait command signal to the processor during the processor's operating cycle.

The operating cycle of the processor is synchronized with the system clock supplied to the processor, and one operating cycle is defined as several cycles of the system clock. In conventional wait control methods, the operating cycles of a processor are extended by inserting a certain number of system clocks into a series of operating cycles consisting of several cycles. For example, if there is 1 wait, one system cycle is taken during the -i operation cycle, and if there is 2 waits, 2 cycles are taken.
Each is inserted unconditionally to extend the operation cycle.

Here, even if the time to be secured for memory access or I10 access is, for example, a half cycle or a quarter cycle of the system clock cycle, if it is 1 wait, it will be 1 cycle or 2 waits. If so, two cycles are inserted unconditionally. That is,
Since the system clock is always extended by an integer number of cycles, it increases wasted time, makes it impossible to secure efficient operating cycles, and reduces processor throughput. There are drawbacks.

Purpose of the Invention The present invention has been made to solve the above-mentioned drawbacks of the conventional ones, and its purpose is to improve the throughput of a processor by ensuring an efficient operation cycle. The object of the present invention is to provide a possible weight control method.

According to the present invention, the present invention includes a basic clock generating means, and a system clock generating means that divides the basic clock using a frequency divider to generate a system clock for determining the operating cycle of the processor. The wait control method extends the operation cycle period of the processor in response to a command signal, the frequency divider is reset in response to the wait command signal, and the frequency divider is reset in response to the termination of the wait command. Thus, a weight control method is obtained, characterized in that the reset of the frequency divider is released in synchronization with the basic clock.

Example Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

In the figure, an oscillator 1 generates a basic clock, and this basic clock is divided into 1/4 by a frequency divider 2 and supplied to a clock driver 3. This clock driver 3 supplies a system clock that determines the operating cycle of the processor to each circuit. On the other hand, a reset pulse generation circuit 4 is provided to perform reset control of the frequency divider 2, and generates a reset pulse in response to a wait instruction input. Specifically, as shown in the time chart of FIG. 2, when a wait instruction signal (WAIT) is input, the processor states (equal to the system clock cycle) are counted, and a predetermined number (equal to the system clock cycle) is counted. In the example, the number of states is 2 (T2 and T3), a reset pulse is generated.

After that, the reset pulse is also terminated in response to the end timing of the wait instruction input, and at this time, the frequency divider 2 starts dividing the basic clock again in synchronization with the basic clock, and the system clock occurrence is resumed. As a result, as shown in FIG. 2, in the processor state T3, the operating cycle of the processor is apparently extended, for example, by one period of the basic clock (T14).

In the conventional weight control method, as shown in "Conventional State" in FIG. 2, a wait is applied in state T3 in response to a wait instruction input, as in the case of the present invention, but even if it is only 1 wait, If the system clock is
Since a weight of only cycle TW3 is applied, the throughput decreases as described above.

In contrast, in the present invention, wait control is performed by reset control of the frequency divider 2 that generates the system clock, so the operating cycle time of the processor can be extended by the period truly necessary for the wait, thereby reducing throughput. We can expect improvement.

Effects of the Invention As described above, according to the present invention, since the system clock given to the processor is controlled by the timing of the basic clock, the apparent processor weight can be changed to the basic clock unit whose cycle is faster than that of the system clock. Therefore, it is possible to operate the processor efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the blocks in FIG. Explanation of symbols of main parts 1... Oscillator 2... Frequency divider

Claims (1)

[Claims] (1) A basic clock generating means; a system clock generating means for dividing the basic clock by a frequency divider to generate a system clock for determining the operating cycle of the processor; The wait control method extends the operation cycle period of the frequency divider, wherein the frequency divider is reset in response to the wait command signal, and synchronized with the basic clock in response to the end of the wait command. The weight control method is characterized in that the reset of the frequency divider is canceled when the frequency divider is reset.