JPH01178646U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 is a block diagram of one embodiment of the present invention;
The figure is a system diagram of the shared bus system, Figure 3a, Figure 3.
FIG. b is a timing chart of the embodiment, and FIG. 4 is a state transition diagram of the embodiment. 1...Bus request generation circuit, 2...Logic circuit,
3...Request arbitration circuit, 4...Priority determination circuit.

Claims (1)

[Claim for Utility Model Registration] A shared bus arbitration circuit that arbitrates requests for shared bus use from multiple microprocessors, including a bus request generation circuit that outputs a bus request signal for each microprocessor; A circuit that logically ANDs the processor's bus request signal and the negation of the bus grant signal for the microprocessor and outputs it as a pending bus request signal using an open collector type driver, and a cloth on the bus that wire-ORs this output. and request arbitration for outputting a bus grant signal that allows the microprocessor whose bus request signal is set to "1" to continue acquiring the right to use the bus when the pending request signal from each of the microprocessors is "0". A shared bus arbitration circuit characterized by comprising a circuit and.