JPH036741U - - Google Patents

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Publication number
JPH036741U
JPH036741U JP6721189U JP6721189U JPH036741U JP H036741 U JPH036741 U JP H036741U JP 6721189 U JP6721189 U JP 6721189U JP 6721189 U JP6721189 U JP 6721189U JP H036741 U JPH036741 U JP H036741U
Authority
JP
Japan
Prior art keywords
bus
counting
arbitration circuit
counting means
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6721189U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6721189U priority Critical patent/JPH036741U/ja
Publication of JPH036741U publication Critical patent/JPH036741U/ja
Pending legal-status Critical Current

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  • Bus Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案一実施例の要部構成図、第２図
は本考案の一実施例を示す概略構成図である。 １，２，３，４……バスマスタ、５，６，７…
…バススレーブ、８……バス、９……優先順位制
御部、１０……バスアービタ部、１１，１４，１
５，１６……ブロツク１，２，３，４、１２……
カウンタ、１３……優先順位生成ロジツク、１７
，１８，１９，２０……ラツチ回路。 FIG. 1 is a block diagram of a main part of an embodiment of the present invention, and FIG. 2 is a schematic block diagram showing an embodiment of the present invention. 1, 2, 3, 4... bus master, 5, 6, 7...
... Bus slave, 8 ... Bus, 9 ... Priority control section, 10 ... Bus arbiter section, 11, 14, 1
5, 16...Block 1, 2, 3, 4, 12...
Counter, 13...Priority generation logic, 17
, 18, 19, 20...Latch circuit.

Claims (1)

【実用新案登録請求の範囲】 (1) 同一のバスに接続された複数のバスマスタ
のバス使用権を調停するバス調停回路において、 各バスマスタからのバス使用の要求の回数を計
数する計数手段と、該計数手段の計数結果に応じ
て各バスマスタのバス使用の優先順位を決定する
優先順位制御手段とを備えることを特徴とするバ
ス調停回路。 (2) 前記計数手段の計数値を所定時間毎に初期
値に戻すタイマ手段を備えることを特徴とする請
求項１記載のバス調停回路。[Claims for Utility Model Registration] (1) In a bus arbitration circuit that arbitrates bus usage rights among multiple bus masters connected to the same bus, a counting means for counting the number of bus usage requests from each bus master; 1. A bus arbitration circuit comprising: priority control means for determining bus use priority for each bus master according to the counting result of the counting means. 2. The bus arbitration circuit according to claim 1, further comprising timer means for returning the count value of the counting means to an initial value at predetermined time intervals.
JP6721189U 1989-06-08 1989-06-08 Pending JPH036741U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6721189U JPH036741U (en) 1989-06-08 1989-06-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6721189U JPH036741U (en) 1989-06-08 1989-06-08

Publications (1)

Publication Number Publication Date
JPH036741U true JPH036741U (en) 1991-01-23

Family

ID=31600586

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6721189U Pending JPH036741U (en) 1989-06-08 1989-06-08

Country Status (1)

Country Link
JP (1) JPH036741U (en)

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