JPH01180152A - Frame synchronizing system - Google Patents

Abstract

PURPOSE:To stabilize the circuit operation and to reduce the synchronization restoration time by operating block and frame synchronization of a specific code independently at a low speed. CONSTITUTION:An N-bit is takes as one block, a code converting one block into M-bit is used, a serial parallel conversion circuit 3 converts the inputted data signal to the input terminal 1 by using N-phase clock signal frequency- divided by a 1/N frequency division circuit 4 into a parallel signal and outputs it to a block synchronization detection circuit 10 and a frame pulse detection circuit 11 and also output terminals 9a-9n. Then the circuit 10 controls the 1/N frequency divider circuit 4 till the block synchronizing signal is detected from the N-set of parallel signals and it is executed till the block synchronization is taken. Then the circuit 11 detects the frame pulse from the N-set of parallel signal and outputs the count start signal to the frame counter 12. Thus, the counter 12 is operated by the count start signal input. Then the synchronization establish is discriminated by the operation start of the counter 12.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a digital communication system using an optical fiber transmission line as a medium and inserting optical repeaters at appropriate intervals into the medium.
In particular, the present invention relates to a frame synchronization method that can stabilize circuit operation.

[Conventional technology]

Conventionally, this type of frame synchronization method used flip-flop circuits equal to the number of synchronization pulses, and the synchronization pulses were detected every time. However, as the information transmission speed increases, the system requires elements that operate at high speed. , circuit feasibility was extremely difficult. Next, it became necessary to synchronize the signal by converting it into several parallel signals.

FIG. 2 is a circuit diagram showing a conventional frame synchronization method. In the figure, 1 is an input terminal to which a data signal is input, 2 is a clock input terminal to which a clock is input, 3 is a serial-to-parallel conversion circuit that converts the input data signal into N parallel signals, and 4 is a clock input terminal to which N phase signals are input. N to divide the clock signal into
A frequency dividing circuit, 5 is a synchronization pattern detection circuit that outputs a mismatch pulse when the synchronization pattern of N parallel signals is at a different position from the frame pulse input from the 7-frame counter 6, and T is a synchronization pattern detection circuit that outputs a mismatch pulse when this mismatch pulse is input. a gate circuit for shifting the phase of the frame counter 6 by stopping the clock generated by the N frequency divider circuit 4 by one time;
N parallel signals are rearranged in order and output terminal 9 ~
The operation of the frame synchronization method with the above configuration will be explained in 1. First, the serial-to-parallel conversion circuit 3 divides the data signal input from the input terminal IK by the N frequency divider circuit 4. The synchronous pattern detecting circuit 5 converts the 9 N-phase clock signals into parallel signals and outputs them to the synchronous pattern detecting circuit 5 and the signal switching circuit 8. Therefore, the synchronous pattern detecting circuit 5 converts the synchronous non-turns of the N parallel signals into 7 parallel signals. When the frame pulse position is different from the signal indicating the frame pulse position sent from the frame counter 6, a mismatch pulse is output to the gate circuit T. When a mismatch pulse is input, this gate circuit T stops the clock generated by the N frequency divider circuit 4 by one clock and shifts the phase of the frame counter 6, and the position is confirmed in the synchronization pattern detection circuit 5. Repeat until. When synchronization is achieved, a control signal is sent from the synchronization pattern detection circuit 5 to the signal switching circuit 8, and the N parallel signals are rearranged in a condylar order and output.

[Problem to be solved by the invention]

The conventional frame synchronization method described above has the drawback that the operation within the synchronization pattern detection circuit is fast, making it difficult to implement the circuit, and furthermore, the circuit becomes extremely complex when the speed is reduced.

[Means to solve the problem]

The frame synchronization method according to the present invention operates independently of each other the block synchronization means for synchronizing blocks of NBMB codes and the frame synchronization means for detecting frame pulses and synchronizing frames. The circuit scale can be reduced and the synchronization recovery time can be shortened.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the frame synchronization method according to the present invention. In the figure, reference numeral 10 denotes a block synchronization detection circuit for an NBMB code, which controls the N frequency divider circuit 4 until a block synchronization signal is detected from N parallel signals;
1 is a frame pulse detection circuit that detects frame pulses from these N parallel signals and outputs a count start signal;
Reference numeral 12 represents a frame counter which performs a counting operation upon input of this count start signal, and reference numeral 13 represents an output counter.

Next, the operation of the frame synchronization method with the above configuration will be explained. First, the serial-to-parallel conversion circuit 3 converts the data signal input to the input terminal 1 into a parallel signal using the N-phase clock signal frequency-divided by the N-frequency divider circuit 4, and converts the data signal input to the input terminal 1 into a parallel signal using the block synchronization detection port wr10 and the frame pulse detection @path. 11 and output terminals 91 to 9n. Therefore, the block synchronization detection circuit 10 controls the N frequency divider circuit 4 until it detects a block synchronization signal from these N parallel signals, and continues until block synchronization is achieved. The frame pulse detection circuit 11 detects frame pulses from the N parallel signals and outputs a count start signal to the 7-frame counter 12. Therefore, the frame counter 12 operates upon input of this count start signal. By starting the operation of the frame counter 12, it can be determined that synchronization has been established.

〔Effect of the invention〕

As explained in detail above, according to the frame synchronization method according to the present invention, it is possible to operate at a low speed (by operating the block synchronization and frame synchronization of the NBMB code independently of each other), thereby improving circuit operation. 0, which has the effect of shortening stabilization and synchronization recovery time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the frame synchronization method according to the present invention, and FIG. 2 is a circuit diagram showing a conventional frame synchronization method.・Clock input terminal, 3
...Serial-to-parallel conversion circuit 4 * * Order 11N frequency divider circuit, 9&~9n ...Φ・Output terminal, 10.Fist...Block synchronization detection, circuit, 11...Frame detection circuit, 12Il...・Frame counter, 13. Output terminal. Patent application filed NEC Corporation

Claims (1)

[Claims] In a digital communication system using an NBMB code in which N bits are made into one block and one block is converted into M bits, a block synchronization means synchronizes the blocks of the NBMB code, and a frame synchronization means detects frame pulses and synchronizes the frame. 1. A frame synchronization method, comprising: means for operating the block synchronization means and the frame synchronization means independently of each other.