JPH01181571A - Conduction modulation type mosfet - Google Patents

Abstract

PURPOSE:To avoid a latch-up phenomenon by a method wherein the flow of electrons is provided from an electron emitter electrode to a semiconductor layer through a source layer and a channel region and the flow of positive holes are provided from the semiconductor layer to a positive hole emitter electrode through a body layer so as to be independent from each other. CONSTITUTION:As a positive hole emitter electrode 24 and an electron emitter electrode 22 are independently formed on a base layer 10 and a source layer 15 respectively, the flow of electrons is provided from the electron emitter electrode 22 to a semiconductor layer 11 through the source layer 15 and a channel region 16. On the other hand, the flow of the positive holes is provided from the semiconductor layer 11 to the positive hole emitter electrode 24 through a body layer 14. Therefore, the positive hole current and the electron current can be separately taken out. With this constitution, a latch-up phenomenon can be suppressed and controlled without exerting particular influence upon an ON resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate bipolar transistor (Insulated Gate B 1P) which is used as a power switching element, for example.
olar Translator: IGB
The present invention relates to a conduction modulation type MO3FET configured with T).

[Prior Art] Power switching elements are required to have both high breakdown voltage and low on-resistance, and as elements that satisfy these conditions, conductive An insulated gate bipolar transistor (hereinafter abbreviated as IGBT), which is a modulation type MO8FET, has been developed.

However, this IGBT has a parasitic thyristor inside the element, and when the collector current increases, the parasitic thyristor turns on, and even if the voltage applied to the gate is changed, the collector current cannot be controlled. A latch-up phenomenon occurs.

In order to solve such problems, for example,
As shown in Japanese Patent Application No. 196974, a highly concentrated impurity layer is formed directly under the source region. Also,
As shown in Toshiba Review, Vol. 40, No. 5 (1985), No. 427, countermeasures such as irradiation with neutron beams or electron beams have been considered.

However, with such means, the collector current (latch-up current) when a latch-up phenomenon occurs increases, but at the same time, the on-resistance also increases. The relationship between the on-resistance and the latch-up current of this element differs depending on the conditions for making the cord, and is determined by the person making the element.

[Problems to be Solved by the Invention] This invention has been made in view of the above points, and provides conductive modulation that effectively prevents the latch-up phenomenon without affecting the on-resistance. Type MO8FE
The aim is to provide T.

In addition, the present invention has a self-diagnosis function that allows the mutual relationship between on-resistance and latch-up current to be arbitrarily selected, and that ensures that the device is not destroyed due to the latch-up phenomenon. An object of the present invention is to provide a conductivity modulation type MO3FET that can be set.

[Means for Solving the Problems] That is, in the conductivity modulation type MOSFET according to the present invention, a body of a second conductivity type with a low impurity concentration is formed on a semiconductor substrate of a first conductivity type, and In the conductivity modulation type MO3FET, a base layer of the first conductivity type is formed on the surface of the body, and a source layer of the second conductivity type is formed by leaving a channel region on the surface of the base layer. A gate electrode is set via a gate insulating layer corresponding to the channel region, and a hole emitter electrode is formed on the surface of the body layer, and an electron emitter electrode is formed on the surface of the source layer. It is something.

Further, the hole emitter electrode is grounded, and the hole emitter electrode and electron emitter electrode are connected through a resistor circuit, and the hole emitter current and electron emitter current are connected to each other through a resistor circuit. This makes it possible to monitor relative relationships.

[Function] In the gate insulated bipolar transistor configured as described above, a hole emitter electrode and an electron emitter electrode are formed independently in each of the base layer and the source layer. The flow of electrons is set from the electron emitter electrode through the source layer and channel region to the semiconductor layer, and the flow of hole current is set from the semiconductor layer through the body layer to the hole emitter electrode. This allows the hole current and electron current to be extracted separately to the outside of the device. Therefore, the collector current when the latch-up phenomenon occurs can be increased in accordance with the value of the resistance circuit connecting the hole emitter electrode and the electron emitter electrode, and the hole current and electron current can be increased. The occurrence of latch-up phenomenon can be detected from the relative relationship with

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1(a) shows the cross-sectional structure of an insulated gate bipolar transistor, which is a conductivity modulation type MO8FET.The structure will be explained according to the manufacturing process.
First, a p+ semiconductor substrate 11 with a high impurity concentration is set.

On the surface of this p-type semiconductor substrate 11, an n+ buffer layer 12 with a high impurity concentration for producing holes is formed by epitaxial growth, and then an n'' base layer with a low impurity concentration is formed. 13 is formed by epitaxial growth.

For the substrate lO on which the buffer layer 12 and base layer 13 have been formed by double epitaxial growth on the semiconductor substrate ti in this way, a gate insulating film 20 of 8102 or the like is formed, and then polysilicon, metal silicide A conductive layer is formed by et al., and the gate electrode IT is formed by patterning this conductive layer.

Once the gate electrode 17 is formed in this way, ion implantation and drive-in are performed using the gate electrode 17 as a mask.
A p-type body layer 14 and an n+ type source layer 15 are formed by the elf A llgn) method.

After the body layer 14 and source layer 15 are formed in this way, 5102, P
An interlayer insulating layer 21 is formed of SG%BPSG or the like, and the electron emitter electrode 22 is electrically insulated from the body layer 14 and connected to the source layer 15.
Formed by 1st class.

Then, layer 10 is further formed using 5IO2, 513N4, etc.
A, ii', A, ff-51 insulating layer 23 is formed, and the hole emitter electrode 24 is insulated from the electron emitter electrode 22 and connected to the body layer 14.
Formed by etc.

The hole terminal Eh connected to the hole emitter electrode 24 is connected to a ground circuit, and the electron terminal Ee connected to the electron emitter electrode 22 is connected to the hole terminal Eh.
is connected to via a variable resistor Rv.

19 is a collector electrode.

FIG. 1(b) shows the symbol of the IGBT configured as described above.

In a general IGBT, when the collector current becomes large as mentioned above, the collector current cannot be controlled even if the voltage applied to the gate G is changed due to the parasitic silis that is built into the IGBT. An unavoidable latch-up phenomenon will occur.

However, in the IGBT configured as above,
When the control voltage is applied to the gate electrode 17,
An electron current 1c flows from the electron emitter electrode 22 from the n+ source layer 15 toward the n- base layer 13 via the channel region IB formed directly under the gate electrode 17. This electron current biases the pn junction formed by the n+8777 layer 12 and the p-type semiconductor substrate 11 in the forward direction, and the hole current flows from the n+ base layer 13 to the pn junction directly below the n+ source layer 15. It flows through the body layer 14 toward the hole emitter electrode 24 .

Here, the collector current becomes large and the condition under which the latch-up phenomenon occurs in the general IGBT described above, that is, Ih value) Under the conditions, the n+ source layer 15 and the p body layer 14
The potential difference ΔVnp between ΔVnp and ΔVnp is expressed by the following equation.

ΔVnp -1h be.

, and by connecting the variable resistor Rv between the hole emitter electrode 24 and the electron emitter electrode 22,
The on-resistance of this IGBT is slightly sacrificed.

Therefore, when actually using this IGBT, the relationship between the collector current value and on-resistance that causes the latch-up phenomenon should be arbitrarily selected depending on the user's usage conditions. Therefore, it is effective if the value of the variable resistor Rv can be arbitrarily selected and set to meet the user's requirements.

Note that this variable resistor Rv only needs to have a constant resistance value after the relationship between the latch-up current value and the on-resistance is set, so it should be a semi-fixed resistor or a resistor formed on a semiconductor chip Any structure may be used as long as the resistor thin film is trimmed.

FIG. 2(a) shows an embodiment in which a part of the power and a sensor part are formed, and the ratio of the number of unit cells of the part of the power and the sensor part is n:1. The symbol is set as shown in FIG. 2(b).

In the IGBT according to this embodiment, part of the power is
It has a structure similar to that of a general IGBT as shown in the figure, and includes a body layer 141 and a source layer 151 formed corresponding to the surface portion of the base layer 13, and a gate electrode 17 and an emitter electrode 18. is starting to form. The emitter electrode 18 has an emitter terminal E.
is connected to the gate electrode 17, and a gate electrode G is connected to the gate electrode 17.

Further, the sensor section has a structure similar to that shown in FIG.
52 and the body layer 142, an electron emitter electrode 22 and a hole emitter electrode 24, which are insulated from each other, are connected, respectively, and the hole emitter electrode 24 is configured in common with the emitter electrode 18. ing.

Figure 3 shows an equivalent circuit of an IGBT configured in this way. When a control voltage is applied to the gate G, the current flowing through the entire chip is divided into the power part and the sensor part. The current will be divided at a ratio of :1. This shunted current is an electronic current flowing through one IGBT unit cell! When expressed by e and hole current 1h, a current of "n(1e"+Ih)'s flows in the power part, and a current of "(1(+'+Ih)"') flows in the sensor part.

When latch-up occurs in this circuit,
That is, when all of the npn) run risks in the equivalent circuit shown in FIG. 4 are turned on, the electron current flowing through the electron emitter electrode 22 increases rapidly.

In order to suppress such a latch-up phenomenon, the gate voltage applied to the gate electrode 17 may be cut off before the npn) run lister is turned on. Therefore, by forming a protection circuit as shown in FIG. 4 in the IGBT as shown in FIG. 2(a), it is possible to prevent the latch-up phenomenon from occurring.

This protection circuit is suitable for IGBT as shown in FIG.
The hole emitter current flowing to the hole terminal Eh of 100 and the electron emitter current flowing to the electron terminal Ee are detected as terminal voltages of resistors R1 and R2, respectively, and these voltage values are compared and amplified by an operational amplifier OP. ing. Then, it detects a state in which the electronic current flowing to the electronic terminal Ee rapidly increases, and controls the MOS) run lister 200 to turn on,
Both ends of the power source El are short-circuited to cut the voltage applied to the gate of the IGBTloo.

In other words, the IGBT with this protection circuit has a self-diagnosis function that cuts the gate voltage when a latch-up phenomenon occurs and prevents the latch-up phenomenon from occurring. It is what it is.

[Effects of the Invention] As described above, the conductivity modulation type MOSF E' according to the present invention
In T, the occurrence of latch-up phenomenon can be suppressed and controlled without particularly affecting the on-resistance, and in particular, the relationship between the collector current at which the latch-up phenomenon occurs and the on-resistance can be selectively set. It becomes like this. In addition, by monitoring the hole current and electron current, it is possible to set a self-diagnosis function that detects situations where latch-up occurrence conditions are set and shuts off the gate voltage. This allows transistors to be used effectively.

[Brief explanation of the drawing]

FIG. 1(a) shows the cross-sectional structure and components of one embodiment of the present invention, FIG. 1(b) shows the symbol mark of the above embodiment, and FIG. 2(a) shows another embodiment of the present invention. FIG. 2(b) is a cross-sectional diagram showing the embodiment, FIG. 2(b) is a diagram showing its symbol mark, FIG. 3 is a diagram showing its equivalent circuit, and FIG. 4 is a diagram showing a self-diagnosis circuit. 11...Semiconductor substrate (p+ type), 12...n+ buffer layer, 13.n- base layer (semiconductor layer), 14.14
1. 142 ・f) Body layer, 15.151 , 152 ・
n◆source layer, 1B...channel region, I7...gate electrode, 18...emitter electrode, 22...electron emitter electrode, 24...hole emitter electrode, Rv...
resistance. Applicant's agent Patent attorney Takehiko Suzue Figure 2 (a) Figure 2 (b)

Claims (3)

[Claims] (1) A semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on this semiconductor substrate and having a low impurity concentration, and a first conductivity type semiconductor layer formed corresponding to a surface portion of this semiconductor layer. a semiconductor body layer of a conductivity type; a source layer of a second conductivity type formed such that a channel region is set within a region of the body layer corresponding to the surface portion thereof; and a source layer of a second conductivity type corresponding to the channel region. a gate electrode formed on the surface of the semiconductor layer via a gate insulating layer, and a hole emitter electrode and an electron emitter electrode formed to be coupled to the surface of the body layer and the surface of the source layer, respectively. The flow of electrons is separated from the electron emitter electrode to the semiconductor layer via the source layer and the channel region, and the flow of hole current is separated from the semiconductor layer to the hole emitter electrode via the body layer. A conductivity modulation type MOSFET characterized in that the conductivity modulation type MOSFET is configured to
. (2) a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on this semiconductor substrate and having a low impurity concentration; and a first semiconductor layer formed corresponding to the surface portion of this semiconductor layer. a semiconductor body layer of a conductivity type; a source layer of a second conductivity type formed such that a channel region is set within a region of the body layer corresponding to the surface portion thereof; and a source layer of a second conductivity type corresponding to the channel region. a gate electrode formed on the surface of the semiconductor layer via a gate insulating layer, and a hole emitter electrode and an electron emitter electrode formed to be coupled to the surface of the body layer and the surface of the source layer, respectively. A conductivity modulation type MOSFET comprising: the hole emitter electrode is grounded, and the hole emitter electrode and the electron emitter electrode are connected by a resistance circuit. (3) a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on this semiconductor substrate and having a low impurity concentration; and a first semiconductor layer formed corresponding to the surface portion of this semiconductor layer. a semiconductor body layer of a conductivity type; a source layer of a second conductivity type formed such that a channel region is set within a region of the body layer corresponding to the surface portion thereof; and a source layer of a second conductivity type corresponding to the channel region. A gate electrode is formed on the surface of the semiconductor layer via a gate insulating layer, and a gate electrode is formed so as to be coupled to each of the surface of the body layer and the surface of the source layer, and is set to be insulated from each other. a hole emitter electrode and an electron emitter electrode, and means for comparing a current flowing through the hole emitter electrode and a current flowing through the electron emitter electrode, and a means for comparing a current flowing through the electron emitter electrode with a current flowing through the electron emitter electrode. A conductivity modulation type MOSFET characterized by detecting an increase in voltage and cutting off a voltage applied to a gate electrode.