JPH01183152A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To largely reduce a range required for connection and to easily integrate a semiconductor memory by forming a conductive layer on the upper end of the inner face of a trench, and connecting the charge storage electrode of a capacitor through the conductive layer to a transistor. CONSTITUTION:A charge storage electrode 29 is connected to a transistor by a conductive layer 28 and an N<+> type diffused layer 31 formed on the upper end of the inner face of a trench 26. Accordingly, a range required for this connection becomes a range equals the thickness of the layer 28 plus the depth of the layer 31. Thus, since a cell contact is formed in the depthwise direction along the trench, the length of the contact can be largely reduced, and it can be easily integrated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device such as a dynamic type memory that can be read and written at any time (DRAM), and a method for manufacturing the same, and particularly relates to a connection portion between a capacitor and a control transistor. It is related to.

(Prior art) Conventionally, as a technology in this field, IEDM85 (
IEEE>, (1985) (US) P, 710-713.

Hereinafter, its structure and manufacturing method will be explained using the drawings.

FIG. 2 is a sectional view showing the structure of a conventional semiconductor memory device, and FIG. 3 is an enlarged view of section A in FIG.

This semiconductor memory device is a BSE (Buried S
It is an MO8 type semiconductor dynamic storage device called a storage electrode (vertical storage electrode) cell. This semiconductor memory device is formed on a silicon (Si) substrate].
is formed by P+ type upper and lower layers 2 containing a high concentration of boron (B) and a P type layer 3 formed thereon and containing B at about IE15 to 5E16 cm-1.

Above the P-type layer 3 of the Si substrate 1, there is a P-type layer 3 as an element isolation region.
A + type diffusion layer 4 and an oxide film 5 are sequentially formed. Near these sides, trenches 6 are formed that penetrate the P type layer 3 and reach the P+ type upper and lower base layers 2. A dielectric layer 7 is formed on the inner surface of the trench 6, and a charge storage electrode 8 is embedded in the trench 6 in which the dielectric layer 7 is formed. These dielectric layer 7 and charge storage electrode 8 form a capacitor.

A conductive layer 9 is formed on the trench 6 through a part of the oxide film 5.
is formed, and an insulating film 10 is formed on the conductive layer 9. A cell contact 11 on the charge storage electrode 8 side is formed at a location where the conductive layer 9 contacts the charge storage electrode 8, and a cell contact 11 on the transistor side is formed at a location where the conductive layer 9 contacts an N+ type diffusion layer 12 formed outside the trench 6. A contact 13 is formed.

The N+ type diffusion layer 12 is the N+ type diffusion layer 12 of the transistor consisting of the N+ type diffusion layer 14, the gate insulating film 15, and the gate electrode 16.
It is connected to the + type diffusion layer 14.

Therefore, the charge storage electrode 8 and the N+ type diffusion layer 14 of the transistor are connected via the conductive layer 9 and the above-furnace diffusion layer 12. The N+ type diffusion layer 14 of the transistor is N+
It is connected to a conductor 18 for wiring via a shaped diffusion layer 17 . Note that an insulating film 19 is formed on the gate electrode 16, and an insulating film 20 is further formed thereon.

In the semiconductor memory device configured as described above, charge transfer is controlled by turning on and off the transistor, and data is written to and read from the capacitor.

Next, a method for manufacturing the above semiconductor memory device will be explained.

First, P is applied to the surface of the Si substrate 1 on which the P type layer 3 is grown on the P+ type upper and lower layers 2 by a selective oxidation method (LOCO8 method) or the like.
An element isolation region consisting of a + type diffusion layer 4 and an oxide film 5 is formed. Next, a trench 6 having a depth of about 4 to 5 μm is formed by a reactive ion etching method (RIE method) or the like, and then the inner surface of the trench 6 is coated with 5i02, Si3N4.
A dielectric M7 made of a 5i02 multilayer film is formed. Thereafter, polysilicon is buried in the trench 6 to form a charge storage electrode 8.

Next, the entire surface of the Si substrate 1 is oxidized to grow an oxide film 5, and then the oxide film 5 is patterned by a photolithography process to form openings for cell contacts 11 and 13. Next, polysilicon is grown on oxide film 5 including the openings for cell contacts 11 and 13, and this polysilicon is further patterned by a photolithography process to form conductive layer 9. At this time, N-type diffusion [12] is formed by diffusion of impurities contained in the polysilicon.

Thereafter, by performing existing transistor forming steps, wiring forming steps, etc. using known techniques, a semiconductor memory device as shown in FIG. 2 can be obtained.

(Problems to be Solved by the Invention) However, the semiconductor memory device having the above structure and its manufacturing method have the following problems in terms of high integration of elements and manufacturing process.

(i) In the semiconductor memory device having the above configuration, a predetermined area for the cell contacts 11 and 13 is required, and for this purpose, as shown in FIG. Strict accuracy is also required for the length ΔL. Therefore, it is difficult to reduce the element size.
This was a major obstacle in achieving higher integration.

(ii) In the above manufacturing method, two photolithography steps are required to form the cell contacts 11.13, which complicates the manufacturing process and
The amount of man-hours required for this was also large.

The present invention provides a semiconductor memory device and a manufacturing method thereof that solves the problems of the prior art, such as difficulty in achieving high integration and complicated manufacturing process.

(Means for Solving the Problems) In order to solve the above problems, a first invention provides a dielectric layer formed on the inner surface of a trench formed in a semiconductor substrate, and a dielectric layer formed on the inner surface of a trench formed in a semiconductor substrate. A semiconductor memory device comprising: a capacitor having a charge storage electrode embedded in the trench; and a transistor connected to the charge storage electrode to control charge transfer to the capacitor;
A conductive layer having approximately the same thickness as the dielectric layer is formed at the upper end of the inner surface of the trench, and the charge storage electrode and the transistor are connected through the conductive layer.

Further, a second aspect of the present invention is to form a dielectric layer on the inner surface of a trench formed in a semiconductor substrate, and to form a capacitor by burying a charge storage electrode in the trench in which the dielectric layer is formed. In a method of manufacturing a semiconductor memory device, the transistor is formed at an upper end of an inner surface of the trench after the charge storage electrode is embedded in the trench. The step of removing the dielectric layer, and the step of burying a conductor in the gap formed by removing the conductor layer to form a conductive layer for connecting the charge storage electrode and the transistor are performed. This is what I did.

(Function) According to the first invention, since the semiconductor memory device is configured as described above, the conductive layer formed at the upper end of the inner surface of the trench and having approximately the same thickness as the dielectric layer serves as a connection between the capacitor and the transistor. It functions to perform this on the contact surface along the depth direction of the trench.

Due to this function, the length of the connection portion in the direction of the surface of the semiconductor substrate is significantly reduced.

In addition, in the manufacturing method of the second invention, the dielectric layer formed at the upper end of the inner surface of the trench is removed, and the conductive layer is embedded in the gap formed by this removal, so the number of times the photolithography process is performed can be reduced. In addition to making it possible to reduce the amount of the conductive layer, it also serves to facilitate the formation of the conductive layer.

Therefore, the above problem can be eliminated.

(Embodiment) FIG. 1 is a sectional view of a semiconductor memory device showing an embodiment of the first invention, and FIG. 4 is an enlarged view of section B in FIG. 1.

The Si substrate 21 is composed of P+ type upper and lower layers 22 and a P type layer 23 formed thereon.

An element isolation region consisting of a P+ type diffusion layer 24 and an oxide film 25 is formed on the P type layer 23, and in the vicinity of the side thereof, a region having a depth that penetrates the P type layer 23 and reaches the P+ type base Jii22 is formed. A trench 26 of about 4 to 5 μm is formed.

The inner surface of the trench 26 is made of, for example, 5i02°Si.
A dielectric plate 27 made of a multilayer film of N5i02 and having a thickness of about 34×200 to 300 layers is formed. On one side of the upper end of the inner surface of the trench 26, the dielectric layer 27 is removed and a conductive layer 28 is formed in its place. The conductive layer 28 is made of polysilicon or the like containing phosphorus (P) or arsenic (As), and has approximately the same thickness as the dielectric layer 27.

A charge storage electrode 29 made of polysilicon containing P or As is embedded in the trench 26 inside the dielectric layer 27 and the conductive layer 28 . Charge storage electrode 29
At the contact point between the conductive layer 28 and the cell contact 30
is formed.

Further, the conductive layer 28 is located on the inner surface of the trench 26, that is, on the Si substrate 2.
1, there is an N+ layer on the P-type layer 23 side.
A type diffusion layer 31 is formed, and this N+ type diffusion layer 31
The contact surface between the conductive layer 28 and the conductive layer 28 forms a cell contact 32. An oxide film 33 is formed on the trench 26 in a range extending from the oxide film 25 to the N+ type diffusion layer 31.

The N+ type diffusion layer 31 is the N+ type diffusion layer 31 of the transistor consisting of an N+ type diffusion [34, a gate insulating film 35, and a gate electrode 36].
It is connected to the + type diffusion layer 34.

Therefore, the charge storage electrode 29 and the N+ type diffusion layer 34 of the transistor are connected via the cell contact 30.32. The N type diffusion layer 34 of the transistor is connected to a wiring conductor 38 via an N+ type diffusion layer 37. Note that an insulating film 39 is formed on the gate electrode 36, and an insulating film 40 is further formed thereon.

In the above embodiment, the conductive N28 and N-type wave dispersion layer 31 formed on the upper end of the inner surface of the trench 26 provide
Since the two charge storage electrodes are connected to the transistor, the range required for this connection is the sum of the thickness T of the conductive layer 28 and the depth D of the N+ type diffusion layer 31, as shown in FIG. Become.

Here, the thickness T is about 200 to 300 people, and the thickness D
is about 0.2 to 0.5 μm, so the range can be significantly reduced compared to the conventional method.

Unfortunately, if the conventional length and ΔL in FIG. 3 are set to 0.8 .mu.rrt and 0.3 .mu.m, respectively, the connection range can be reduced to about 1/7 to 1/3 compared to the conventional connection range.

Therefore, there is an advantage that the semiconductor memory device can be highly integrated and that strict accuracy such as the length ΔL is not required.

FIGS. 5(a) to 5(f) are manufacturing process diagrams of a semiconductor memory device showing an embodiment of the second invention.

This manufacturing process consists of first to sixth steps in order to obtain the semiconductor memory device shown in FIG.

(1) First step in FIG. 5(a) First, P of the Si substrate 21 containing boron (B>) at a high concentration.
B on the carved stratum 22 at IE15~5E16cm-,1
The P-type layer 23 is grown to a thickness of about 2 μm.

On this P-type layer 23, a P-type scattering layer 24 and an oxide film 25 are formed by LOCO8 method or the like. At that time, the oxide film 25
The trench 26 is grown to a thickness of about 4,000 to 6,000 layers, and then a trench 26 having a depth of about 4 to 5 μm and a width of about 1 μm, for example, is formed by RIE method or the like.

(2) Second step in Figure 5(b) 5i02, Si3, N4 on the inner surface of the trench 26.

The dielectric material N27 consisting of a multilayer film of S i O2 has a thickness of 20
Form to about 0 to 3008. Next, polysilicon containing P or As is grown by low-pressure chemical vapor deposition (LPCVD) or the like, and then etched back to leave the polysilicon only in the trenches 26 to form charge storage electrodes 29.

This forms a capacitor.

(3) Third step in FIG. 5(C) Next, the entire surface is oxidized to grow an oxide film 33, and then a resist film 41 for patterning is formed on the oxide film 33.

The steps up to this point are performed almost in the same manner as in conventional semiconductor memory device manufacturing methods.

(4) Fourth step in FIG. 5(d) The oxide film 33 is patterned by performing a photolithography process using the resist film 41, and an opening 42 is formed at a location including the end portion above the trench 6. When this frontage 42 is formed, the dielectric layer exposed within the opening 42 is also etched, and the dielectric layer 27 is removed to a depth of, for example, about 3000 to 5000 mm. As a result, a gap 43 is formed in the portion where the dielectric layer 27 has been removed.

(5) Fifth step in FIG. 5(e) Next, after removing the resist film 41, polysilicon 44 containing P or As is grown on the entire surface by LPCVD or the like. At this time, the gap 43 is also filled with polysilicon 44, and the conductive layer 28 is formed. After the polysilicon 44 has grown, RIE using a fluorine (F) gas or the like is performed to remove the polysilicon 44 in areas other than the gap 43.

(6) After removing the polysilicon 44 in the sixth step of FIG. 5(f), an oxide film 33 is grown on the entire surface. An N-type diffusion layer 31 is formed in the P-type layer 23 in contact with the conductive layer 28 by diffusion of impurities from polysilicon, and this N+-type diffusion layer 31 connects the conductive layer 28 and the contacts formed on both sides thereof. It is connected to the charge storage electrode 29 via 30 and 32.

Thereafter, in the state shown in FIG. 5(f), the oxide film 33 in the transistor formation region is removed and a normal transistor formation process is performed. That is, as shown in FIG. 1, a gate insulating film 35 is formed by thermal oxidation, and a gate electrode 36 is formed by patterning the N-type diffused polysilicon formed by the LPCCVD method. Furthermore, an N swelling diffusion layer 34 is formed by P 2 or As ion implantation using the gate electrode 36 as a mask, and an oxide film is grown at the same time as the heat treatment for activating the N swelling diffusion layer 34 to insulate the P 2 or As ion implantation.
Form A39.

Next, as a wiring formation process, atmospheric pressure vapor phase epitaxy (APC) was used.
Growth of 5i02 containing P and B by VD method etc., opening of a contact hole, formation of an N expansion diffusion layer 37 by ion implantation into the contact 1 hole, deposition and patterning of a wiring conductor 38 made of metal. By performing the above steps, the semiconductor memory device shown in FIG. 1 can be obtained.

According to the above-described manufacturing method, when forming the cell contacts 30 and 32 for connecting the capacitor and the transistor, it is possible to reduce the complicated process to one time, which was conventionally required twice. In addition, conventionally
Since the cell contacts, which were previously formed on the plane of the substrate 21, are formed in the depth direction along the trenches 26, the length of the contact portions can be significantly reduced, and high integration can be easily achieved.

Note that the semiconductor memory device and the method for manufacturing the same according to the first and second inventions are not limited to the illustrated embodiments, and can be modified in various ways. For example, the format or structure of the transistor, trench 26, etc. may be changed, or the materials forming each part may be changed. Furthermore, it is also possible to change the conditions, manufacturing order, etc. in each manufacturing process.

(Effects of the Invention) As described above in detail, according to the semiconductor memory device of the first invention, a conductive layer is formed on the upper end of the inner surface of the trench, and the charge storage electrode of the capacitor and the transistor are formed via the conductive layer. Therefore, the range required for this connection is greatly reduced, and high integration of the semiconductor memory device can be easily achieved.

Further, according to the manufacturing method of the second invention, the dielectric layer formed at the upper end of the inner surface of the trench is removed, and a conductive layer connecting the capacitor and the transistor is formed in the gap formed by the removal. This has the advantage that the manufacturing process is simplified by reducing the number of times the photolithography process is performed, and that a semiconductor memory device that can easily be highly integrated can be manufactured.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor memory device showing an embodiment of the first invention, FIG. 2 is a sectional view of a conventional semiconductor memory device, FIG. 3 is an enlarged view of section A in FIG. 2, and FIG. Enlarged view of part B in Figure 1,
and FIGS. 5(a) to 5(f) are manufacturing process diagrams of a semiconductor memory device showing an embodiment of the second invention. 21...Si substrate, 26...trench, 27... Dielectric layer, 28... Conductive layer, 29... Charge storage electrode, 31, 34.37.
...N swelling diffusion layer, 35...gate insulating film, 36...gate electrode. Applicant's agent: Kyo Kakimoto Sei 21: 3L board 26: Trench 27: Attraction @ stop layer Cross-sectional view of the f-control I21 planned installation Fig. 2 Enlarged view of part A Fig. 3 Fig. 1 Figure 2 Scabbard Enlarged view of part B of Figure 1 Figure 4

Claims (1)

[Scope of Claims] 1. A capacitor having a dielectric layer formed on the inner surface of a trench formed in a semiconductor substrate, and a charge storage electrode embedded in the trench in which the dielectric layer is formed, and the charge storage electrode. In a semiconductor memory device comprising a transistor connected to a storage electrode and controlling charge transfer to the capacitor, a conductive layer having approximately the same thickness as the dielectric layer is formed at an upper end of the inner surface of the trench, and the conductive layer is A semiconductor memory device characterized in that the charge storage electrode and the transistor are connected through a layer. 2. Forming a dielectric layer on the inner surface of a trench formed in a semiconductor substrate, burying a charge storage electrode in the trench in which the dielectric layer is formed, and forming a capacitor;
In the method of manufacturing a semiconductor memory device, the transistor is connected to the charge storage electrode and controls charge transfer to the capacitor. the step of removing the dielectric layer; and the step of burying a conductor in the gap formed by removing the dielectric layer to form a conductive layer for connecting the charge storage electrode and the transistor. A method of manufacturing a semiconductor memory device, characterized in that: