JPH0118424B2 - - Google Patents

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Publication number
JPH0118424B2
JPH0118424B2 JP54115700A JP11570079A JPH0118424B2 JP H0118424 B2 JPH0118424 B2 JP H0118424B2 JP 54115700 A JP54115700 A JP 54115700A JP 11570079 A JP11570079 A JP 11570079A JP H0118424 B2 JPH0118424 B2 JP H0118424B2
Authority
JP
Japan
Prior art keywords
recording
layer
electrode
voltage
electrostatic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54115700A
Other languages
Japanese (ja)
Other versions
JPS5640846A (en
Inventor
Takashi Ezaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP11570079A priority Critical patent/JPS5640846A/en
Publication of JPS5640846A publication Critical patent/JPS5640846A/en
Publication of JPH0118424B2 publication Critical patent/JPH0118424B2/ja
Granted legal-status Critical Current

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  • Dot-Matrix Printers And Others (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
  • Electrophotography Using Other Than Carlson'S Method (AREA)

Description

【発明の詳細な説明】 この発明は、静電記録方式において高品質の記
録画像を低廉なコストで得るための改良に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement for obtaining high quality recorded images at low cost in an electrostatic recording method.

従来、ピン電極等を用いて記録媒体に静電記録
を行なう場合、記録ドツト径の異常に大きなもの
が発生するなどして、解像度の低い記録画像しか
得られないという問題があり、この問題解決のた
めに既に幾つかの提案がなされている。
Conventionally, when performing electrostatic recording on recording media using pin electrodes, etc., there was a problem that only recorded images with low resolution could be obtained due to abnormally large recording dot diameters, etc.This problem was solved. Several proposals have already been made for this purpose.

第1図イは、かかる従来の提案になる静電潜像
形成方式(特開昭53−147532号公報)を示す概略
図であり、第1図ロはその電気的な等価回路を示
す回路図である。同図を参照する。潜像形成体
は、導電基材3上に、第1の誘電体層である下地
層4として、その静電容量C2が低くかつ中間的
な抵抗R2をもつ層をコーテイングし、更に電荷
潜像の形成される記録層として、第2の誘電体層
から成る高静電容量C1の記録層5を形成した二
層構成のものを用い、ピン電極1にドライバー2
からパルス電圧を印加することにより記録層5に
潜像を形成する。下地層4の静電容量C2は、記
録層5の静電容量C1より低く、少なくとも数分
の1程度に選定しておく。すると、ピン電極1か
らパルス電圧を印加した場合、その印加中に、時
定数C2R2で決まる周期で複数回放電電流が断続
し、良好な潜像ドツトが得られるというものであ
る。しかしこの従来例においては、記録層5の静
電容量C1より低い静電容量C2をもつ下地層4を
実現することは、実際上困難であるという欠点が
ある。一般に樹脂にカーボン等を混ぜて導電性を
もたせると静電容量が非常に大きくなるものであ
り、従つて上述の下地層4の実現は事実上難しい
と云える。
FIG. 1A is a schematic diagram showing the electrostatic latent image forming method proposed in the past (Japanese Patent Application Laid-Open No. 147532/1983), and FIG. 1B is a circuit diagram showing its electrical equivalent circuit. It is. Refer to the same figure. The latent image forming body is made by coating a conductive base material 3 with a layer having a low capacitance C 2 and an intermediate resistance R 2 as a first dielectric layer 4, and then applying a charge. As a recording layer on which a latent image is formed, a two-layer structure is used, in which a recording layer 5 of high capacitance C 1 is formed of a second dielectric layer, and a driver 2 is connected to a pin electrode 1.
A latent image is formed on the recording layer 5 by applying a pulse voltage. The capacitance C 2 of the underlayer 4 is selected to be lower than the capacitance C 1 of the recording layer 5, and at least a fraction of the capacitance C 1 . Then, when a pulse voltage is applied from the pin electrode 1, the discharge current is intermittent multiple times at a period determined by the time constant C 2 R 2 during the application, and a good latent image dot can be obtained. However, this conventional example has a drawback in that it is practically difficult to realize the underlayer 4 having a capacitance C 2 lower than the capacitance C 1 of the recording layer 5. Generally, when a resin is mixed with carbon or the like to impart conductivity, the capacitance becomes extremely large, and therefore it can be said that it is practically difficult to realize the above-mentioned base layer 4.

第2図は、同じく従来の提案に係る静電記録装
置の回路構成図(特公昭52−19414号公報)であ
る。同図においては、背面電極6、前面電極7、
高電圧電源8、静電記録用媒体9、前面電極の突
起部分10が図示の好く配置され、背面電極6と
高電圧電源8のアース側端子との間に抵抗rを介
在させている。この回路構成で抵抗rの抵抗値を
100kΩ以上30MΩ以下に設定し、電極7と6の
間に電圧パルスを印加したところ、抵抗rの存在
しない場合に比し、良好な静電記録を得たという
ものである。しかしこの従来例のように、抵抗r
を外部回路につなぐと、漂遊容量との関係で記録
速度が遅くなり、高速記録には適しないという欠
点がある。ちなみに、漂遊容量を100PFとし、抵
抗10MΩとすると、時定数は100×10-12×10×
106=10-3秒となる。
FIG. 2 is a circuit diagram of an electrostatic recording device according to a conventional proposal (Japanese Patent Publication No. 19414/1983). In the figure, a back electrode 6, a front electrode 7,
A high voltage power source 8, an electrostatic recording medium 9, and a protruding portion 10 of the front electrode are arranged as shown in the figure, and a resistor r is interposed between the back electrode 6 and the ground terminal of the high voltage power source 8. With this circuit configuration, the resistance value of resistor r is
When a voltage pulse was applied between electrodes 7 and 6 with the resistor set at 100 kΩ or more and 30 MΩ or less, better electrostatic recording was obtained than in the case where the resistor r did not exist. However, as in this conventional example, the resistance r
If it is connected to an external circuit, the recording speed will be slow due to the stray capacitance, which has the disadvantage that it is not suitable for high-speed recording. By the way, if the stray capacitance is 100PF and the resistance is 10MΩ, the time constant is 100×10 -12 ×10×
10 6 = 10 -3 seconds.

第3図は、従来の提案にかかる静電記録体の略
断面図(特開昭50−152733号公報)である。同図
に示されたものは、導電性基板11と誘電体から
成る静電記録層12との間に、106〜1012Ω・cm
の体積固有抵抗を有しかつ数μ〜数+μの厚さを
有する半導電性の中間層13を介在させた記録体
であつて、具体的には、導電性基板11をアルミ
ニウムにより構成し、該アルミの基板上にアルマ
イト処理を施して半導電性の中間層13を形成
し、その上に誘電体層12を設けて成る記録体で
あり、かかる記録体を用いて静電記録を行なえば
画品質の向上を図り得るというものである。しか
し、この場合にも、第1図について説明した従来
例の場合と同様、実際問題として上述のような中
間層13を伴つた誘電体層12の実現は困難であ
るという欠点がある。またアルマイト処理により
中間層を形成するのでは抵抗値が高すぎて静電記
録の効率が悪いという欠点がある。
FIG. 3 is a schematic cross-sectional view of an electrostatic recording medium according to a conventional proposal (Japanese Unexamined Patent Publication No. 152733/1983). The one shown in the figure has a resistance of 10 6 to 10 12 Ω·cm between the conductive substrate 11 and the electrostatic recording layer 12 made of a dielectric material.
The recording medium has a semiconductive intermediate layer 13 interposed therebetween and has a volume resistivity of several μ to several + μ, and specifically, the conductive substrate 11 is made of aluminum, This is a recording medium in which a semiconductive intermediate layer 13 is formed by alumite treatment on the aluminum substrate, and a dielectric layer 12 is provided on top of the semiconductive intermediate layer 13, and when electrostatic recording is performed using such a recording medium, This means that image quality can be improved. However, in this case as well, as in the case of the conventional example described with reference to FIG. 1, there is a drawback in that, as a practical matter, it is difficult to realize the dielectric layer 12 with the intermediate layer 13 as described above. Furthermore, forming the intermediate layer by alumite treatment has the drawback that the resistance value is too high and the efficiency of electrostatic recording is poor.

第4図は、同じく従来の提案にかかる静電記録
方式(1978年11月16日電子写真学会第42回研究討
論回におけるプリント)を示す概要図である。同
図では、ポリエステルフイルムなどから成るベー
ス18と、ポリエステル樹脂に顔料を加えて成る
誘電層16との中間に、金属蒸着膜から成る導電
層17を配置した記録体を用い、記録電極14に
電圧V1を、また制御電極15に電圧V2を印加す
ることにより静電記録を行なう方式であるが、こ
の方式はいわゆる片面記録方式と呼ばれるもので
記録速度が遅いという欠点がある。すなわちこの
方式は、記録速度が数m3/ライン以上という遅い
記録の場合に適し、高速記録には適しないという
欠点がある。
FIG. 4 is a schematic diagram showing an electrostatic recording method similarly proposed in the past (printed at the 42nd research discussion session of the Electrophotography Society, November 16, 1978). In the figure, a recording medium is used in which a conductive layer 17 made of a metal vapor deposition film is arranged between a base 18 made of a polyester film or the like and a dielectric layer 16 made of a polyester resin with pigment added, and a voltage is applied to the recording electrode 14. This method performs electrostatic recording by applying voltage V 1 and voltage V 2 to the control electrode 15, but this method is a so-called single-sided recording method and has the drawback of slow recording speed. That is, this method has the disadvantage that it is suitable for slow recording at a recording speed of several m 3 /line or more, but is not suitable for high-speed recording.

また、静電潜像を形成される誘電体層の面とピ
ン電極を非接触で対向させ、ピン電極に電圧を印
加して両者間に放電を起こさせることにより誘電
体層面に静電潜像を形成する静電記録装置の場
合、誘電体層の面とピン電極が非接触(両者間に
空隙がある)であるので、ピン電極に印加する電
圧を高くしないと放電が起きなくなる。このよう
な事情でピン電極に印加する電圧を高くすると、
ピン電極相互間の耐圧の点でピン電極の高密度配
列が困難となり、そのため記録密度を上げること
ができず、高品質の記録画像が得られないとか、
同様にピン電極に印加する電圧が高くなると、近
接電極への誘導電圧の影響が大きくなり、やはり
高品質の記録画像が得られないという問題点を生
じる。またピン電極に印加する電圧を高くする
と、回路素子に高耐圧のものが必要になり、コス
トが高くなるという問題もある。これらの問題点
を解決するため、従来提案された静電記録装置
(特開昭50−158336号)は、誘電体層面に予め一
様に電荷を帯電させ、放電に必要な電界強度を、
帯電電荷に起因する誘電体層表面電圧とピン電極
に印加する電圧とに分担させることにより、ピン
電極に印加する電圧を低減させるものであつた。
しかしこの記録装置では、誘電体層面に予め電荷
を帯電させる方法として、コロナ放電を別に起こ
してそれにより発生した電荷を帯電させる方法を
採つており、誘電体層面に帯電むらが起き易く、
そのため記録画像の画質が安定しないという欠点
がある。
In addition, the surface of the dielectric layer on which the electrostatic latent image is formed is opposed to the pin electrode in a non-contact manner, and a voltage is applied to the pin electrode to cause discharge between the two, thereby creating an electrostatic latent image on the surface of the dielectric layer. In the case of an electrostatic recording device in which the surface of the dielectric layer and the pin electrode are not in contact (there is a gap between them), discharge will not occur unless the voltage applied to the pin electrode is increased. Under these circumstances, if the voltage applied to the pin electrode is increased,
It is difficult to arrange the pin electrodes in a high density arrangement due to the withstand voltage between the pin electrodes, which makes it impossible to increase the recording density and make it impossible to obtain high-quality recorded images.
Similarly, when the voltage applied to the pin electrode increases, the influence of the induced voltage on the adjacent electrode increases, resulting in the problem that a high quality recorded image cannot be obtained. Furthermore, if the voltage applied to the pin electrode is increased, circuit elements with high withstand voltages are required, resulting in an increase in cost. In order to solve these problems, the electrostatic recording device previously proposed (Japanese Patent Application Laid-Open No. 158336/1983) uniformly charges the surface of the dielectric layer in advance to reduce the electric field strength necessary for discharge.
The voltage applied to the pin electrode was reduced by sharing the voltage applied to the pin electrode with the dielectric layer surface voltage caused by the charged charges.
However, in this recording device, as a method for pre-charging the surface of the dielectric layer, a method is used in which a corona discharge is generated separately and the resulting charge is charged, which tends to cause uneven charging on the surface of the dielectric layer.
Therefore, there is a drawback that the quality of recorded images is unstable.

この発明は、上述した如き従来の諸提案例の欠
点を解決するためになされたものであり、従つて
この発明の目的は、高速記録が可能であると共
に、記録ドツト径が拡大したりせず正常な大きさ
であるため解像度が高く、その上、実際問題とし
て実現が容易であり、また記録画像の画質を不安
定にすることなく記録電極の印加電圧を低減させ
ることのできる静電記録方式を提供することにあ
る。
This invention was made in order to solve the drawbacks of the conventional proposals as described above, and the purpose of this invention is to enable high-speed recording and to prevent the recording dot diameter from increasing. An electrostatic recording method that has high resolution due to its normal size, is easy to implement in practice, and can reduce the voltage applied to the recording electrode without destabilizing the quality of the recorded image. Our goal is to provide the following.

この発明の構成の要点は、誘電体からなる記録
層と絶縁体からなる絶縁層との中間に導電性の抵
抗体からなる抵抗層を配置して成る記録体におい
て、前記抵抗層の一端を一定電位源に接続し、前
記記録層には記録電極を対向させ、該記録電極と
前記一定電位源との間で、前記記録層と抵抗層を
介して放電電流を流して前記記録層に静電潜像を
形成するようにし、その際、静電潜像を形成する
に必要な電界強度を、前記抵抗層に印加する一定
電位の電圧と前記記録電極に印加する電圧とに分
担させ、かつ前記記録電極と前記記録層との間の
空隙による静電容量が前記記録層のもつ静電容量
より小さく、かつ前記抵抗層の表面抵抗が105
1012Ω/□であるようにした点にある。
The main point of the structure of the present invention is that in a recording medium in which a resistance layer made of a conductive resistor is arranged between a recording layer made of a dielectric material and an insulating layer made of an insulator, one end of the resistance layer is A recording electrode is connected to a potential source, and a recording electrode is opposed to the recording layer, and a discharge current is passed between the recording electrode and the constant potential source through the recording layer and the resistance layer to generate an electrostatic charge in the recording layer. A latent image is formed, at which time the electric field strength necessary to form the electrostatic latent image is shared between a constant potential voltage applied to the resistive layer and a voltage applied to the recording electrode, and The capacitance due to the gap between the recording electrode and the recording layer is smaller than the capacitance of the recording layer, and the surface resistance of the resistance layer is 10 5 to 10.
10 12 Ω/□.

次に図を参照してこの発明の実施例を説明す
る。第5図はこの発明の一実施例を示す概要図で
あり、第6図は同じく他の実施例を示す概要図で
あり、第7図はその電気的等価回路を示す回路図
である。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 5 is a schematic diagram showing one embodiment of the present invention, FIG. 6 is a schematic diagram showing another embodiment, and FIG. 7 is a circuit diagram showing an electrical equivalent circuit thereof.

第5図を参照する。記録体は、誘電体等よりな
る記録層19と絶縁体等よりなる絶縁層21とそ
れらの中間に配置された導電性の抵抗層20とか
ら成るものを用いており、ピン電極等からなる記
録電極22は、記録層19に対し接触または
100μm以下の微小間隙を設けた(以下、単に非
接触という)状態で対向するものであるが、第5
図では接触した場合を示す。また記録体は絶縁ロ
ーラ24により支持されている。導電性の抵抗層
20の一端を電源VBを介して接地する。一端を
接地されたパルス電圧源23からパルス電圧を記
録電極22に印加すると、点線で示した如き放電
電流の流れる閉回路が出来る。すなわち、パルス
電圧源23から記録電極22、記録層19、抵抗
層20、電源VBを通つてパルス電圧源23に戻
る閉回路が出来る。放電電流の大きさは導電性の
抵抗層20の表面抵抗値により規定される。また
放電電圧はパルス電圧源23からの電圧と電源
VBの電圧により分担される。
Please refer to FIG. The recording medium is composed of a recording layer 19 made of a dielectric material or the like, an insulating layer 21 made of an insulator or the like, and a conductive resistance layer 20 placed between them. The electrode 22 is in contact with or in contact with the recording layer 19.
They face each other with a minute gap of 100 μm or less (hereinafter simply referred to as non-contact), but the fifth
The figure shows the case of contact. Further, the recording medium is supported by an insulated roller 24. One end of the conductive resistance layer 20 is grounded via a power supply VB. When a pulse voltage is applied to the recording electrode 22 from a pulse voltage source 23 whose one end is grounded, a closed circuit in which a discharge current flows as shown by the dotted line is created. That is, a closed circuit is formed from the pulse voltage source 23 through the recording electrode 22, the recording layer 19, the resistive layer 20, and the power source VB and returning to the pulse voltage source 23. The magnitude of the discharge current is determined by the surface resistance value of the conductive resistance layer 20. In addition, the discharge voltage is the voltage from the pulse voltage source 23 and the power supply.
It is shared by the voltage of VB.

第6図を参照する。記録電極22と記録層19
は非接触であり、記録体は金属ドラム25により
支持されている点で第5図の実施例と相違する。
放電時の放電電流が抵抗層20の表面抵抗値によ
り規定され、また放電電圧がパルス電圧源23か
らの電圧と電源VBの電圧により分担される点は
同じである。
Please refer to FIG. Recording electrode 22 and recording layer 19
This embodiment differs from the embodiment shown in FIG. 5 in that it is non-contact and the recording medium is supported by a metal drum 25.
Similarly, the discharge current during discharge is defined by the surface resistance value of the resistance layer 20, and the discharge voltage is shared by the voltage from the pulse voltage source 23 and the voltage from the power supply VB.

第7図を参照する。同図に示す等価回路におい
て、静電容量Caは記録電極22と記録層19と
の間の微小空隙による容量であり、Cbは誘電体
から成る記録層19のもつ静電容量であり、抵抗
Rは抵抗層20の表面抵抗である。また静電容量
Cnは、記録体の支持に金属ドラム25を用いた
場合、つまり第6図の実施例の場合に生じる容量
であり、第5図の実施例の場合には生じない容量
であるから、この意味で破線で表現してある。
Please refer to FIG. In the equivalent circuit shown in the figure, capacitance C a is the capacitance due to the microgap between the recording electrode 22 and the recording layer 19, C b is the capacitance of the recording layer 19 made of dielectric material, The resistance R is the surface resistance of the resistance layer 20. Also capacitance
C n is the capacity that occurs when the metal drum 25 is used to support the recording medium, that is, in the case of the embodiment shown in FIG. 6, and is the capacity that does not occur in the case of the embodiment shown in FIG. It is represented by a broken line for its meaning.

以上に示した如き、この発明の実施例の構成に
おいて、導電性抵抗層20の表面抵抗値Rを変え
ることにより、或いは該抵抗層20の接地位置を
調整することにより、記録層19における静電潜
像ドツトの拡大、ぼけ、にじみ等、記録画像の解
像度を劣化させる要因を容易に取り除くことがで
きる。また静電容量CbをCaより大きくするのが
よく、またそれは容易である。抵抗層20の表面
抵抗105〜1012Ω/□が適当である(ここで、□
は一般的に一辺が1cmの正方形を表す)。
In the configuration of the embodiment of the present invention as described above, the electrostatic charge in the recording layer 19 can be reduced by changing the surface resistance value R of the conductive resistance layer 20 or by adjusting the grounding position of the resistance layer 20. Factors that degrade the resolution of recorded images, such as enlargement of latent image dots, blurring, and blurring, can be easily removed. Furthermore, it is preferable and easy to make the capacitance C b larger than C a . A suitable surface resistance of the resistance layer 20 is 10 5 to 10 12 Ω/□ (here, □
generally represents a square with sides of 1 cm).

次に具体例を述べると、記録層19としては、
ポリエステル10〜30μm厚程度のものが適当であ
るが、中に高誘電率の粒子を分散させる等の方法
で静容量を大きくすれば膜厚をさらに厚くしても
記録効率は低下しない。また表面に耐磨耗層を付
加すれば耐久性を向上できる。導電性の抵抗層2
0としては、パラジウム、酸化インジウム等の金
属あるいは金属酸化物等の蒸着膜を用いるとよ
く、表面抵抗は105〜1012Ω/□が適当である。
また蒸着以外のスパツタリングまたはイオン導電
性樹脂を使用することも可能である。絶縁層21
としては、ポリエステル200μm厚が適当である
が、絶縁体であれば他のどんなものでもよく、膜
厚も適宜のものを選択してよい。ただ第6図の実
施例の場合のように、下に金属体が位置する場合
は、膜厚を適当に選ぶことにより記録の効率の向
上を図ることが可能である。つまり等価回路にお
ける静電容量Cnによる効果がみられるわけであ
る。
Next, to describe a specific example, the recording layer 19 is as follows:
A polyester film with a thickness of about 10 to 30 μm is suitable, but if the capacitance is increased by a method such as dispersing particles with a high dielectric constant therein, the recording efficiency will not decrease even if the film thickness is further increased. Additionally, durability can be improved by adding an abrasion resistant layer to the surface. conductive resistive layer 2
0, a metal such as palladium, indium oxide, or a vapor-deposited film of a metal oxide may be used, and a suitable surface resistance is 10 5 to 10 12 Ω/□.
It is also possible to use sputtering other than vapor deposition or ion conductive resin. Insulating layer 21
A suitable thickness of polyester is 200 μm, but any other insulating material may be used, and the film thickness may be selected as appropriate. However, as in the case of the embodiment shown in FIG. 6, when a metal body is located below, it is possible to improve the recording efficiency by appropriately selecting the film thickness. In other words, the effect of the capacitance C n in the equivalent circuit can be seen.

第8図は、記録電極とアース(GND)間にか
かる電圧VGの時間的変化を示すグラフである。
同図において、電源VBの電圧VB=0の場合は、
放電開始は、電圧VGが放電スレシユホールド電
圧Vthを超える時刻t2であるが、適当な電圧VB
(≠0)を印加しておくと、時刻t1で電圧VGは放
電スレシユホールド電圧Vthを超える。すなわち
静電記録開始の時刻が早まる。但しこの場合、
VB<Vthであることが必要である。なおVPは、
記録電極に印加される電圧を表わす。
FIG. 8 is a graph showing temporal changes in the voltage VG applied between the recording electrode and the ground (GND).
In the same figure, when the voltage of power supply VB is VB=0,
Discharge starts at time t2 when voltage VG exceeds discharge threshold voltage Vth, but when an appropriate voltage VB
(≠0), the voltage VG exceeds the discharge threshold voltage Vth at time t1 . In other words, the start time of electrostatic recording is advanced. However, in this case,
It is necessary that VB<Vth. In addition, VP is
Represents the voltage applied to the recording electrode.

第9図は、各電圧のレベルを比較して示す電圧
レベル比較図である。同図を参照して、電圧VB
の最適値の決め方を、負帯電の場合を例にとり説
明する。電圧VBは、原則的には放電スレシユホ
ールド電圧Vthに等しくとり得るが、実際には、
他のピン電極に記録電圧が印加されたときに当該
ピン電極に誘起される電圧ViとVBの和がVthを
超えないように、VBを設定するのがよい。Viが
小さければ小さいほど、VBはVthに近ずけ得る
ので記録効率は上昇する。Viを低下させるには、
ピン間の静電容量を小さくする等の工夫をこらす
ことにより実現できる。
FIG. 9 is a voltage level comparison diagram showing a comparison of the levels of each voltage. Referring to the same figure, voltage VB
How to determine the optimum value of will be explained using the case of negative charging as an example. In principle, the voltage VB can be equal to the discharge threshold voltage Vth, but in reality,
It is preferable to set VB so that the sum of voltages Vi and VB induced in the pin electrode when a recording voltage is applied to another pin electrode does not exceed Vth. The smaller Vi is, the closer VB can be to Vth, so the recording efficiency increases. To lower Vi,
This can be achieved by taking measures such as reducing the capacitance between pins.

以上説明した通りであるから、この発明によれ
ば、静電記録方式において解像度の高い鮮明な記
録ドツトを得るのに、そのために必要な記録体の
実現が容易であること、しかも高速記録を維持で
きること、さらに記録電極に印加する電圧を低減
できるので、記録電極駆動回路の絶縁耐力が小さ
くてすみ、その分コストを低廉にできること、記
録電極間隔をせばめ得るので高密度記録が可能と
なり、安定した高品質の画像記録が得られる等の
利点がある。
As explained above, according to the present invention, in order to obtain clear recorded dots with high resolution in an electrostatic recording method, it is easy to realize a recording medium necessary for this purpose, and moreover, it is possible to maintain high-speed recording. Furthermore, since the voltage applied to the recording electrodes can be reduced, the dielectric strength of the recording electrode drive circuit can be reduced, reducing costs accordingly.The distance between the recording electrodes can be narrowed, making high-density recording possible and stable. It has advantages such as high quality image recording.

【図面の簡単な説明】[Brief explanation of drawings]

第1図イは、従来の静電潜像形成方式の一例を
示す概略図であり、ロはその電気的等価回路を示
す回路図、第2図は従来の静電記録装置の回路構
成図、第3図は同じく従来の静電記録体の略断面
図、第4図は従来の静電記録方式を示す概要図、
第5図はこの発明の一実施例を示す概要図、第6
図はこの発明の他の実施例を示す概要図、第7図
は上記実施例の電気的等価回路を示す回路図、第
8図は、記録電極とアース間にかかる電圧の時間
的変化を示すグラフ、第9図は諸電圧のレベルを
比較して示す電圧レベル比較図である。 図において、1はピン電極、2はピン電極ドラ
イバー、3は導電基材、4は第1の誘電体層であ
る下地層、5は第2の誘電体層である記録層、6
は背面電極、7は前面電極、8は高電圧電源、9
は静電記録用媒体、10は前面電極の突起部分、
11は導電性基板、12は静電記録層、13は半
導電性層、14は記録電極、15は制御電極、1
6は誘電層、17は導電層、18はベース、19
は記録層、20は導電性の抵抗層、21は絶縁
層、22は記録電極、23はパルス電圧源、24
は絶縁ローラ、25は金属ドラム、を示す。
FIG. 1A is a schematic diagram showing an example of a conventional electrostatic latent image forming method, B is a circuit diagram showing its electrical equivalent circuit, FIG. 2 is a circuit diagram of a conventional electrostatic recording device, FIG. 3 is a schematic cross-sectional view of a conventional electrostatic recording medium, and FIG. 4 is a schematic diagram showing a conventional electrostatic recording method.
FIG. 5 is a schematic diagram showing an embodiment of the present invention, and FIG.
The figure is a schematic diagram showing another embodiment of the present invention, FIG. 7 is a circuit diagram showing an electrical equivalent circuit of the above embodiment, and FIG. 8 is a diagram showing temporal changes in the voltage applied between the recording electrode and the ground. The graph in FIG. 9 is a voltage level comparison diagram showing a comparison of the levels of various voltages. In the figure, 1 is a pin electrode, 2 is a pin electrode driver, 3 is a conductive base material, 4 is a base layer that is a first dielectric layer, 5 is a recording layer that is a second dielectric layer, 6
is the back electrode, 7 is the front electrode, 8 is the high voltage power supply, 9
10 is the electrostatic recording medium, 10 is the protruding part of the front electrode,
11 is a conductive substrate, 12 is an electrostatic recording layer, 13 is a semiconductive layer, 14 is a recording electrode, 15 is a control electrode, 1
6 is a dielectric layer, 17 is a conductive layer, 18 is a base, 19
20 is a recording layer, 20 is a conductive resistance layer, 21 is an insulating layer, 22 is a recording electrode, 23 is a pulse voltage source, 24
indicates an insulated roller, and 25 indicates a metal drum.

Claims (1)

【特許請求の範囲】 1 誘電体からなる記録層と絶縁体からなる絶縁
層との中間に導電性の抵抗体からなる抵抗層を配
置して成る記録体において、 前記抵抗層の一端を一定電位源に接続し、前記
記録層には記録電極を対向させ、該記録電極と前
記一定電位源との間で、前記記録層と抵抗層を介
して放電電流を流して前記記録層に静電潜像を形
成するようにし、その際、静電滞像を形成するに
必要な電界強度を、前記抵抗層に印加する一定電
位の電圧と前記記録電極に印加する電圧とに分担
させ、かつ前記記録電極と前記記録層との間の空
隙による静電容量が前記記録層のもつ静電容量よ
り小さく、かつ前記抵抗層の表面抵抗が105
1012Ω/□であることを特徴とする静電記録方
式。
[Scope of Claims] 1. A recording medium in which a resistive layer made of a conductive resistor is arranged between a recording layer made of a dielectric material and an insulating layer made of an insulating material, wherein one end of the resistive layer is placed at a constant potential. A recording electrode is placed opposite to the recording layer, and a discharge current is passed between the recording electrode and the constant potential source through the recording layer and the resistance layer to generate an electrostatic latent in the recording layer. In this case, the electric field strength necessary for forming an electrostatic image is divided between a constant voltage applied to the resistive layer and a voltage applied to the recording electrode, and the recording The capacitance due to the gap between the electrode and the recording layer is smaller than the capacitance of the recording layer, and the surface resistance of the resistance layer is 10 5 to 10.
An electrostatic recording method characterized by 10 12 Ω/□.
JP11570079A 1979-09-11 1979-09-11 Electrostatic recording system Granted JPS5640846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11570079A JPS5640846A (en) 1979-09-11 1979-09-11 Electrostatic recording system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11570079A JPS5640846A (en) 1979-09-11 1979-09-11 Electrostatic recording system

Publications (2)

Publication Number Publication Date
JPS5640846A JPS5640846A (en) 1981-04-17
JPH0118424B2 true JPH0118424B2 (en) 1989-04-05

Family

ID=14669058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11570079A Granted JPS5640846A (en) 1979-09-11 1979-09-11 Electrostatic recording system

Country Status (1)

Country Link
JP (1) JPS5640846A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2749608B2 (en) * 1988-12-28 1998-05-13 株式会社リコー Discharge member and charging device using this discharge member

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4877712A (en) * 1972-01-19 1973-10-19
JPH068397B2 (en) * 1986-06-28 1994-02-02 ぺんてる株式会社 Fluorescent water-based ink

Also Published As

Publication number Publication date
JPS5640846A (en) 1981-04-17

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