JPH0118430B2 - - Google Patents

Description

[Detailed description of the invention]

(a) Technical Field of the Invention The present invention relates to a memory control method for controlling access to a display image memory. (b) Prior Art and Problems In a bitmap display device, there is a one-to-one correspondence between a memory location (address) of a display memory where image data is stored and a display position according to the image data stored at that address. In the case of monochrome display, when the signal at a certain memory location in the display memory is "1", the position corresponding to the memory location on the screen is displayed as a bright spot. If the display memory (image memory) is composed of (256×256) bits, for example, access to the display memory is performed in units of bytes (8 bits). Such access takes place in particular when the display memory is composed of a plurality of memory chips. However, such an access method has directionality; for example, it is efficient because 8 bits can be accessed in one access in the horizontal direction, but it is efficient when accessing 8 bits in the vertical direction. , it is necessary to perform horizontal access eight times, resulting in a disadvantage that the number of accesses increases. This will be explained with reference to FIG. Figure 1 has a display memory of (256 x 256) bits, and access is performed in byte (8 bit) units, and in the illustrated example, access is performed horizontally in the order of access units B ₀ , B ₁ ...B ₃₁ . After that, a method is adopted in which data is read by accessing in the horizontal direction from the access unit B ₃₂ in the second row. In this access method, when all 8 bits are signal ``1'' as in access unit B <sub>1</sub> , that is, when displaying horizontal ruled lines, the 1 specified in access unit B <sub>1</sub> is required to read out the 8 bit signal ``1''. Access efficiency is high as only one access is required. On the other hand, in the case of vertical ruled line display, for example, as shown in the figure, the access unit B ₀ ,
If a signal "1" is written to each leftmost bit address of B ₃₂ , B ₁₂₈ , B ₂₅₆ , B ₅₁₂ , B _1K , and B _2K , in order to read these eight signals, the memory There was a drawback that the access to the access unit B ₀ , B ₃₂ , B ₆₄ . . . B had to be repeated eight times while incrementing up to _2K . (c) Purpose of the Invention The present invention has been made to solve the above-mentioned drawbacks, and aims to provide a memory control method that improves the efficiency of accessing display memory. (d) Structure of the invention A processing device having an n-bit data bus D ₀ to _{D o-1} , and an n-bit memory bus J ₀ to _{J o-1} , and the memory is arranged in rows and columns. A memory section configured with elements and connected to each memory element by cyclically switching the memory bus for each row or column, and lower-order signals in the addressing signals X and Y of the memory section output from the processing device. Bit data X', Y' consisting of bit parts are input, and the number of bits of each of these bit data , a switching control unit that outputs switching control data SH according to Y',
A memory control method characterized in that connections between the D ₀ to _{D o-1} data buses and the J ₀ to _{J o-1} memory buses are cyclically switched and connected based on the switching control data SH. It is. (c) Embodiments of the Invention The present invention will be explained below with reference to the drawings, but for convenience of explanation, the number of data buses from the processor 2 will be unified to 8 bits. FIG. 2 is a block diagram explaining the problem of memory access, and FIG. 3 is a block diagram explaining the principle of the present invention to solve this problem. As shown in FIG. 2a, the display memory 1 and processor 2 are 0, 1, 2, ..., 6, 7.
They are connected by eight data buses 3 represented by . It is assumed that the memory 1 is divided into blocks of m rows and n columns, each block consisting of a square of 8.times.8 bits, and access is performed in units of 8 bits in the horizontal or vertical direction. In the case of such a memory 1, eight data buses 3 (D ₀ , D ₁ ,...,
D ₇ ) are combined in the column (horizontal) direction in the order of D ₀ , D ₁ , . . . , D ₇ for each row of 8×8 bits, as shown in FIG. 2b. Note that 8m+0 to 8m+7 are row addresses within the block, and 8n+0 to 8n+7 are column addresses within the block. This connection is similar within memory. For memory 1 combined in this way, one "column" in the vertical direction from processor 2
When accessing in 8-bit units per minute, each address on the same "column" of memory 1 is assigned the same bit of data bus 3 (for example, "column" address 8n+0 of row addresses 8m+0 to 8m+7 has Bit D ₀ of data bus 3 is assigned), so if the ``column'' to be accessed is, for example, the 0th bit ``column'', all 8 bits of the 0th bit ``column'' are supplied from D ₀ of the data bus. The same signal will appear. Therefore, the 0th bit "column"
In order to display the signals supplied by D ₀ to D ₇ of the data bus for each of the first to eighth rows of This is done eight times, and each time it takes time and effort to increment the row address while replacing the signal supplied by bus D ₀ with the signal supplied by D ₁ , D ₂ , . . . D ₇ . Therefore, the present invention provides a memory 1 and a processor 2 as shown in FIG. 3a.
When the memory controller 4 is provided between the memory controller 4 and the memory 1 is accessed horizontally, the memory 1 controls each bit of the data bus 3 horizontally as shown in FIG. 3b when viewed from the data bus 3 side. In contrast, when accessing the memory 1 in the vertical direction, each bit of the data bus 3 in the memory 1 is sequentially coupled in the vertical direction as shown in FIG. 3c. The efficiency of accessing the memory 1 in both horizontal and vertical directions is improved. This can be realized by the memory control unit 4 shown in FIG. 3A switching the connection between the data bus 3 and the memory bus 6. This switching method _is explained in FIG.
Memory bus 6 connected by switching D ₁ ,..., D ₇
The corresponding bits are shown. As shown in Figure 4, the first line of the address within the block (horizontal direction, 8m
+0) are "A'" to "H", and each term of 8m+1 in the next second row is "B" to "A", and so on from row (8m+0) to row (8m+7). is shifted by one position.
This indicates that the memory bus is shifted and connected one by one for each row, and the details will be described later. The connections in the memory 1 shown in FIG.
By making the connections shown in the figure, bit allocation to the memory bus will not be doubled when accessing in either the horizontal or vertical directions. Figure 3a
The access control by the memory control unit 4 in
This will be explained with reference to FIG. The memory 1 and shift control section 5 in FIG. 5 are connected by a memory bus 6, and the shift control section 5 and processor 2 are connected by a data bus 3. The shift control section 5 is composed of selectors S ₁ to _{S 8} as shown in FIG. 6, and the output terminals A to H thereof are connected to the memory bus 6. A shift signal SH from the adder circuit 7 in FIG. 5 is supplied to each of the selectors S ₁ to S ₈ . In addition, each input terminal I ₀ to _{I 7} of selector S ₁ is connected to a data bus as shown in the figure.
D ₀ , D ₇ , D ₆ , D ₅ , D ₄ , D ₃ , D ₂ , D ₁ are connected,
In addition, the data bus is connected to the input terminals I ₀ to I ₇ of selector S ₂ .
D ₁ , D ₀ , D ₇ , D ₆ , D ₅ , D ₄ , D ₃ , D ₂ are connected in a manner that they are shifted by one position. Therefore selector S ₈
The input terminals I ₀ to _{I 7} of the data buses D ₇ , D ₆ , D ₅ ,
D ₄ , D ₃ , D ₂ , D ₁ , and D ₀ are connected. A shift signal SH is supplied to such selectors S ₁ to _{S 7} ,
When the value is "0", output terminal A of selector _S1
is connected to the data bus _D0 , and the output terminal B of the selector _S2 is connected to the data bus _D1 . Below, similar selection connections are made up to selector _S8 , and selector
At _S8 , the output terminal H is connected to the data bus _D7 . The value of shift signal SH is "0" to "7"
When the output terminals A to H of the selectors S ₁ to S ₈ and the data buses D ₀ to _{D 7} are selectively connected in the correspondence shown in the following table.

[Table] The shift signal SH is output from the adder circuit 7,
These are the lower 3 bits X ₀ , X ₁ and X ₂ of the horizontal axis coordinate data X ₀ to _{X 7} indicating the bit position of memory 1 issued from processor 2, and the vertical axis coordinate data Y which also indicates the bit position of memory 1. It is obtained by adding the lower three bits _Y0 to _Y1 and _Y2 of 0 _{to Y7 .} The storage capacity of the memory unit 1 in FIG. 5 is (256
x 256) bits, that is, 65,536 bits, which can be converted into a memory chip of (1 bit x 1024 words).
It consists of 64 pieces. This memory chip (64 pieces)
are arranged in an (8×8) matrix as shown in FIG. 7, and each memory chip receives signals from output terminals A to H of each selector S ₁ to S ₈ shown in FIG. , are supplied in a symmetrical connection relationship to the diagonal terms extending from the upper left to the lower right as shown in FIG. Note that the memory chips (64 pieces) are assigned chip numbers ("0" to "63") as shown in FIG. These memory chips (64 pieces) are selected by the chip selection circuit 9 and selection bus 10 shown in FIG. In addition, the address signal Q from the address decoder 11 and the read/write signal R/from the timing generation circuit 12
W is commonly supplied to 64 memory chips.
The address decoder 11 is a circuit that selects one word from a memory chip (1 bit x 1024 words). This address decoder 11 receives horizontal axis coordinate data _X3 to _X7 and vertical axis coordinate data from the processor 2.
Regarding the values of Y ₃ to _{Y 7} , one word out of 1024 words of each memory chip is determined by 10 bits, with Y ₃ to Y ₇ as the upper 5 bits and horizontal axis coordinate data X ₃ to X ₇ as the lower 5 bits. It outputs an address signal Q for selecting. Note that if this address decoder 11 is built into a memory chip, the above horizontal axis coordinate data
X ₃ to _{X 7} and vertical axis coordinate data Y ₃ to _{Y 7} are supplied to address signal terminals for the memory. The timing generation circuit 12 shown in FIG. 5 is activated by a command (read/write signal R/W) from the processor 2 and outputs a timing signal T. Further, the direction register 13 is a register that stores the direction designation signal P from the processor 2, and the direction designation signal P
is a signal specifying selection of the horizontal axis direction or the vertical axis direction of the memory 1. The chip selection circuit 9 in FIG.
This is a circuit that generates CS ₀ to CS ₆₃ , but this is the 8th
As shown in the figure, fixed storage (64 bits x 128 words)
14 and a gate circuit 15. The fixed storage unit 14 receives the horizontal axis coordinate data X ₀ -X ₂ , the vertical axis coordinate data Y ₀ -Y ₂ and the direction designation signal P from the processor 2 in FIG. 5, and the gate circuit 15 receives the timing signal T. The outputs (chip select signals _CS0 to _CS63 ) are controlled by. The contents of the fixed storage section 14 are as follows. [The value of X ₀ to X ₂ is m, and the value of Y ₀ to _{Y 2} is n. However, O≦m≦7, O≦n≦7] The operation is as follows. (1) When direction signal P is horizontal (“0”) Determined by vertical axis coordinate data Y ₀ to _{Y 2} (8n
+i) A signal “1” is stored in the memory location corresponding to the chip select signal CS (however, i
=0 to 7). For example, when the value of _Y0 to _Y2 of the vertical axis coordinate data is "3" (that is, n=3), the memory (bit) locations corresponding to memory chip numbers "24" to "31" shown in FIG. , the signal is "1". (2) When direction signal P is vertical (“1”) Determined by the value of horizontal axis coordinate data X ₀ to _{X 2}
A signal "1" is stored in the memory location corresponding to the CS signal of 8i+m (however, i=0 to 7). For example, when the value of the horizontal axis coordinate data X ₀ to X ₂ is "6",
Memory chip numbers “6”, “14”, and
A signal "1" is stored in three memory (bit) locations corresponding to "22", "30", "38", "46", "54" and "62". The above is a detailed explanation of each circuit in FIG. 5. Next, the operation of FIG. 5 will be explained. In the bit address of memory 1, the value on the horizontal axis is bit address "6" and the value on the vertical axis is bit address "8".
Let us take as an example the case of writing 8 bits in the vertical direction from the memory location (bit position of the 7th column, 9th row of memory 1). The value according to the horizontal axis coordinate data X ₀ - _{X 2} is "6", the value according to X ₃ - _{X 7} is "0", while the value according to the vertical axis coordinate data Y ₀ - Y ₂ is "0", and the value according to Y ₃ - _Y7
The value of the direction signal P is "1", and the value of the direction signal P is "1" (ie, vertical). The addition circuit 7 performs addition of (X ₀ -X ₂ )+(Y ₀ -Y ₂ ), and the value of the shift signal SH becomes "6". Therefore _, a shift of 6 bits is performed in the shift control section 5. For example, in _the selector _S1 shown in FIG. The connection is made on bus D ₃ and so on. On the other hand, the output Q from the address decoder 11 is configured into a 10-bit pattern (0000100000) with 5 bits of X ₃ to X ₇ (00000) as the lower bits and Y ₃ to _{Y 7} (00001) as the upper bits. Since the binary number pattern is “32” in decimal notation,
“33rd” block, i.e. 8×8 on memory 1 =
2nd block when 64 bits are divided into 1 block
The block corresponding to the first row and column is selected. Further, "vertical" is given to the chip selection circuit 9 as the direction designation signal P, and the value according to the horizontal axis coordinate data X ₀ to X ₂ is "6" and the value according to the vertical axis coordinate data Y ₀ to Y ₂ is "0'', the chip number ``6'' in memory 1 is specified, and from this position vertically ``14'', ``22'', ``30'', ``38'', ``46'', ``
54"
and memory chip "62" is selected. Data buses D ₀ , D ₁ , ..., D ₇ are connected to memory buses "G", "H", "A", to "F" corresponding to the above chip numbers "6" to "62" in that order. Since the data write operation is specified by the read/write signal R/W, and the timing signal T turns ON, writing to the memory chip of the above number is performed at one timing. Figure 9 shows the memory bus 6 in the memory chip.
The connection state of (A, B, C..., H) is shown.
A selection signal from the chip selection circuit 9 shown in FIG. 5 is input to the chip select terminal, and an address signal Q from the address decoder 11 shown in FIG.
and “R/W” from the timing generation circuit 12
The same signal is input to all memory chips. (f) Effects of the Invention As described above, the present invention provides a display memory in which image data is stored, regardless of whether the image data is accessed in the vertical or horizontal direction when reading/writing the image data. Since the data bus is connected in accordance with the address position of the memory to be accessed, it has the advantage of improving the efficiency of access to the display memory.

[Brief explanation of drawings]

Figure 1 is a block diagram of the display memory, Figure 2 is a block diagram explaining memory access, Figure 3 is a block diagram explaining the principle of the present invention, Figure 4 is a connection diagram of the display memory, and Figure 5 is a block diagram explaining the principle of the present invention. 6 is a detailed block diagram of the shift control section 5 in FIG. 5, and FIG. 7 is a block diagram showing the address assignment of the memory chip of the memory 1 in FIG. 5. , FIG. 8 is a detailed block diagram of the chip selection circuit 9 in FIG. 5, and FIG. 9 is a block diagram showing connections between memory chips. The symbols used in the figures are as follows. 1 is a display memory, 2 is a processor, 3 is a data bus, 4 is a memory control section, 5 is a shift control section, 6
is a memory bus, 7 is an adder circuit, 8 is an address bus, 9 is a chip selection circuit, 10 is a selection bus, 11
is an address decoder, 12 is a timing generation circuit, 13 is a direction register, A, B, C, D, E,
F, G, H are selector output terminals, B ₀ , B ₁ ,
B ₃₁ , B ₃₂ , B ₆₄ , B ₁₂₈ , B ₂₅₆ , B ₅₁₂ , B _1K , B _2K are access units, CS ₀ , CS ₆₃ are chip select signals, D ₀ , D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , D ₆ , D ₇ are data buses, I ₀ , I ₁ , I ₂ , I ₃ , I ₄ , I ₅ , I ₆ , I ₇ are selector input terminals, P is a direction designation signal, Q is an address signal, R/W is a read/write signal, SH is a shift signal, T is a timing signal, X ₀ , X ₂ , X ₃ , X ₇ are horizontal axis coordinate data, Y ₀ , Y ₂ , Y ₃ , Y ₇ indicates vertical axis coordinate data.

Claims (1)

[Claims] 1 A processing device having an n-bit data bus D ₀ to D _o-1 and an n-bit memory bus J ₀ to _{J o-1} arranged in vertical and horizontal rows and columns. A storage unit constructed of memory elements and connected to each memory element by cyclically switching the memory bus for each row or column, and each of address designating signals X and Y of the storage unit output from the processing device Bit data X' and Y' consisting of the lower bit parts are input, and the number of bits of each of these bit data ′ _, Y′ _, and a switching control unit that outputs switching control data SH according to the data signals _{SH ;} A memory control method characterized in that the connection is cyclically switched based on the switching control data SH.