JPH0118432B2 - - Google Patents

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a memory control device for graphics, images, etc. data retention;
The present invention relates to a memory control device capable of reading data.

(b) Background of the technology Recently, there has been significant progress in technology for storing, transmitting, storing, and processing document image information, but image information requires more memory than encoded numerical character information. do.

Memories that store this kind of image information, such as optical disks, are being put into practical use, but the technology for displaying this image information on a display has not yet been fully established. is the current situation.

However, the human eye looking at the display will be able to read the original data by, for example, 1/2 in the vertical and horizontal directions.
There is a characteristic that even data that has been thinned out can be read sufficiently, and the present invention was devised by paying attention to this characteristic of the human eye. It is related to the way it is displayed.

(c) Prior art and problems In memory control devices for graphics, image information, etc.
Conventionally, as means for holding thinned data (reduced data) and original data of the information, the original data and thinned data are held in separate memories.
Only original data is held, and if thinned data is required, the original data is read out and thinned data is created through a thinning circuit. There are other methods.
The method (2) has the disadvantage that both memories must be manipulated in order to process figures and images, resulting in a huge amount of processing.The method (2) reads the original data and creates thinned data. However, there was a problem in that the amount of thinned data that could be output per unit time was 1/4 of the original data, which was inconvenient for high-speed processing.

(d) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a method for processing graphic and image information by manipulating only the original data.
To provide a memory control device that can automatically obtain 1/2 thinned data (reduced data) in the vertical and horizontal directions, and to make the amount of information readable per unit time the same for reading the original data and thinned data. The purpose of this invention is to provide a memory control device that can perform the following steps.

(e) Structure of the Invention According to the present invention, an image memory control device is provided which is equipped with a first and a second memory device for holding binary image information, and which comprises a first and a second memory device for holding binary image information. Regarding the information to be stored, the bit string in one word is divided into an even bit string and an odd bit string, and the even bit string and odd bit string in one word are stored in the first memory device and the second memory device, respectively. When displaying at the original density, even bit strings and odd bit strings are read and displayed alternately from both memory devices, and when displaying at 1/2 density, bit strings are read and displayed from one memory device. This is achieved by providing an image memory control device characterized by:

(f) Embodiments of the Invention To summarize the gist of the present invention, the image memory control device of the present invention has two memories that hold figures and images.
Furthermore, the original data of figures and images is divided into even-numbered bit strings and odd-numbered bit strings, and each word is held alternately in the above two banks, and the thinned data or original data is divided into even-numbered bit strings and odd-numbered bit strings. The amount of output per hour is kept constant and the output is selectively made.

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 1 is a diagram showing an example of the configuration of an image data processing system to which the present invention is applied.

In the drawing, 1 is an image memory that holds figures and image information, and is a raster scan type memory.
It also serves as a refresh buffer for CRT display devices. It is assumed that the size of the image memory is a×b bits. 2 is a CRT controller for scanning the screen of a CRT display device (hereinafter referred to as
CRTC), 3 is a raster scan method.
It is a CRT bitmap display (one pixel on the screen corresponds to one bit in the memory), and its resolution is a/2 x b/2 pixels. Therefore, if the image memory data is displayed on the CRT display device 3 after being thinned out by 1/2 vertically and horizontally, the entire image held in the image memory will be reduced to 1/4 and displayed without thinning. If the original data is used, 1/4 of the entire image will be displayed at its original resolution. Reference numeral 4 denotes a high-resolution scanner, and graphics and image information inputted from this scanner are stored in the image memory 1 and become original data. A printer 5 prints out the image information in the image memory 1. Reference numeral 6 denotes a control device for processing image information and screen processing, and usually a microprocessor or the like is used.

In the above system configuration, the contents of the document read from the scanner 4 are stored as original data in the image memory 1, and are further thinned out to 1/2 both vertically and horizontally, and the entire document is displayed in a reduced size on the CRT display device 3. . It is also possible to display the original data without reducing (thinning) a part of the document. (In this case, it can be said to be a combined enlargement.) The reduced data is usually used for screen monitors such as CRTs, and the original data is used for creating high-precision drawings.

Furthermore, in order to perform various conversion processes on the data held in the image memory 1, only the original data needs to be manipulated, and the result is displayed on the CRT display device 3 as a 1/2 thinned image. .

FIG. 2 is a diagram showing a detailed block of the image memory 1 in FIG. 1, and 11 is a memory array section;
21 is a competition control circuit for access from the control device 6 and access from the CRTC 2, and ensures that both accesses do not access the memory array 11 at the same time. A circuit 22 generates an address for the memory array 11 in the case of thinned-out display from the address output from the CRTC 2, and is connected to address selection circuits 16 and 17 shown in FIG. 3, which will be described later. 23 is a memory array 1 that sends data to the control device 6.
This is a buffer of output data from 1 and consists of n bits. Reference numeral 24 designates an output data buffer from the memory array 11 to be sent to the CRT display device 3, and is composed of n bits. 25 displays the original data on the CRT display device 3 or
This is a circuit for selecting whether to display thinned-out data according to an instruction from the control device 6.

In this figure, solid lines indicate data, and dotted lines indicate control signals.

FIG. 3 is a detailed block diagram of the memory array section 11. 12 and 13 are for write data from the control circuit, even bit strings and odd bit strings are 1
This is a 1/2n-bit memory bank that alternately stores words. 14 is an input (write) data switching circuit, which is composed of a 2-input, 1-output multiplexer as shown in FIG. When the address from the control device 6 is an even number, an even number bit string is output, and when the address is an odd number, an odd number bit string is output to the memory bank 1. When is an odd number, an even bit string is output. 15
is an output (read) data switching circuit,
As shown in FIG. 5, if the multiplexer is configured with 3 inputs and 1 output, and no thinning is performed, the lth of both banks (0) 12 and (1) 13 in FIG.
If word data is rearranged and output as shown in Figure 7 and thinned out, the m-th word in bank (0) 12 and the m+1
is an even number) is assembled and output as shown in FIG. 16 is an address selection circuit for bank (0) YZ, which is composed of a 3-input, 1-output multiplexer, and when accessed from the control device 6,
If the address from the control device 6 is accessed from the CRTC2 and there is no thinning, the CRTC
If the address output from CRTC 2 is to be accessed from CRTC 2 and thinned out, CRTC
The address output from 2 is shifted to the left by 1 bit, and "0" is added to the lowest first bit of the address (in other words, the address doubled from the original address), and the address is set to the memory bank ( 0) Output to 12. 17 is an address selection circuit for bank (1) 13, which is composed of a 3-input, 1-output multiplexer, and when accessing from the control device 6, it selects the address from the control device 6 or
When accessing from CRTC2 and without thinning, the address output from CRTC2 is further
When accessing from CRTC2 and thinning out, the address output from CRTC2 is shifted to the left by 1 bit, and "1" is added to the lowest first bit of the address (in other words, the original address is 2
The address multiplied by +1) is output to each memory bank (1) 13 as an address.

The address from CRTC2 and address conversion to each memory bank will be explained in detail in FIGS. 10 and 11.

FIG. 4 is a detailed diagram of the input data switching circuit 14, and ADRSO is the address selection circuit 16, 17.
In the case of a write address from the control device 6, it is the least significant bit of the write address.

FIG. 5 is a detailed diagram of the output data switching circuit 15, and decimation yes and no decimation are selection signals indicating whether or not to perform thinning, respectively, and the access control circuit 21 and display selection in FIG. It is created by circuit 25. ADRSO is the least significant bit of the output address from address selection circuits 16 and 17, and is the address from CRTC2.
When thinning out, the additional bits are used.

FIG. 6 is a diagram showing the correspondence between word numbers of memory bank (0) 12 and memory bank (1) 13 and retained bit numbers when n=16.

FIG. 7 is a diagram showing the arrangement of bit strings of input/output data when n=16 and no thinning is performed, and FIG. 8 is a diagram showing the arrangement of bit strings of output data when thinning is performed. It is.

FIG. 9 is a diagram showing the bit correspondence and address assignment of the image memory 1 as seen from the control device 6 and CRTC 2, and the word numbers in this figure correspond to the word numbers in FIG.

Below, the operation of the image memory unit will be explained separately for access from the control device 6 and access from the CRTC 2.

Access from the control device 6 is always in the form of original data, so in the case of writing,
The bit string data as shown in FIG. 7 is transferred to bank (0) 12 by the input data switching circuit 14 explained in FIGS. 3 and 4, as shown in FIG. 6, when the write address is an even number. Even number bit string data is input to bank (1) 13, odd number bit string data is input to bank (1) 13, and when the write address is an odd number, odd number bit string data is input to bank (0) 12 and bank (1) 13. Even-numbered bit string data is input to each bank and written to each bank.

In the case of reading, as shown in FIG. 6, even number bit string data and odd number bit string data held alternately in two memory banks are
The output data switching circuit explained in the figure rearranges and outputs the bit string as shown in FIG.

Access from the CRTC 2 is for reading only, and if no thinning is performed, the access from the CRTC 2 is exactly the same as the reading when accessed from the control device 6 described above. However, when thinning out, the CRTC2 outputs an address so that the upper left quarter of FIG. 9 becomes the refresh buffer, and the memory bank (0) 12 outputs the bank 0 address in FIG. A value obtained by adding "0" to the lowest first bit of the address obtained by shifting the address from CRTC2 to the left by one bit is supplied as an address via the selection circuit 16, and the third By supplying a value obtained by adding "1" to the lowest first bit of the address obtained by shifting the address from CRTC2 to the left by one bit via the bank 1 address selection circuit 17 shown in the figure, the bank (0 )12,
Only the even bit strings are read from each bank (1) 13, and the output data switching circuit 15 shown in FIGS. 3 and 5 assembles and outputs bit string data as shown in FIG. 8. In this way, out of the memory data shown in FIG. Is displayed.

The above display process will be explained in more detail as follows. That is, in FIG. 9, n=16, a=
If we rewrite the case where 96,b=12 (the number of dots on the display screen is 48×6), the word numbers in the memory will be as shown in FIG.

On the other hand, CRTC2 sequentially outputs the addresses of image memory 1 that holds the data to be displayed, but in this case, the upper left 1/4 part of the above memory (inside the bold line frame in Figure 10) is equivalent to not thinning out. Set it up like this and output it. (This means that the address is output as the refresh buffer mentioned above.) In other words, the address output from CRTC2 is 0,
1, 2, 6, 7, 8, 12, 13, 14, 18,
19, 20, 24, 25, 26, 30, 31, 3
2, 0, 1, 2,... When this address is given to memory devices (0) 12 and (1) 13, it is shifted to the left by 1 bit as described above, and the lowest first
Since 0 and 1 are added to the bits, the addresses actually given to banks 0 and 1 are as shown in Figure 11, and when viewed in Figure 10, they are the words shown in the shaded area, and the vertical direction is also Since each line is read out, and only the even numbered bits of each word are read out in the horizontal direction, the information is thinned out by half in both the vertical and horizontal directions.
It is understood that the image is displayed on a CRT display.

FIG. 12 shows the image memory 1 explained in FIG.
It is a diagram showing the relationship with screen 3 on a CRT display, where screen 3 on the left shows a screen with data without thinning, and screen 3 on the right shows a screen with data thinned out by 1/2 in the vertical and horizontal directions.

As is clear from this figure, the amount of information read out per unit time is the same for reading out the original data and the thinned out data.

As is clear from the above description, according to one embodiment of the present invention, the display of the original data and the thinned-out (reduced) display of image information on the CRT display can be performed using the same memory. Because it is possible to
This has the effect of reducing costs and space, and also has the advantage of improving processing efficiency in image processing, since the results can be displayed as thinned data on a CRT display by manipulating only the original data.

In the present embodiment, a method has been described in which only even-numbered bit strings are read to create 1/2 thinned data in the vertical and horizontal directions, but it goes without saying that the method is not limited to this method.

Furthermore, although the example in which the word numbers of the image memory are assigned in the horizontal direction has been described, it goes without saying that this need not be limited to the horizontal direction either.

(g) Effects of the Invention As described above in detail, the image memory control device of the present invention is capable of retaining vertically and horizontally 1/2 decimated data and original data for image information represented by a binary dot pattern. Since data can be processed within the same memory without duplication, it has the effect of reducing cost and space, and when processing image information, by manipulating only the original data, thinned data can be automatically obtained, improving processing efficiency. This has the effect of improving.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of an image processing system to which the present invention is applied, FIG. 2 is a block diagram showing details of the image memory section shown in FIG. 1, and FIG.
The figure shows the details of the memory array section shown in Fig. 2 as a block diagram, Fig. 4 shows the details of the input data switching circuit as a block diagram, and Fig. 5 shows the details of the output data switching circuit. Figure 6 is a block diagram showing the correspondence between word numbers of the memory device and bit strings held, and Figure 7 is the arrangement of bit strings of input/output data in the memory array section without thinning. FIG. 8 is a diagram showing the arrangement of bit strings of output data from the memory array section when thinning out, FIG. 9 is a diagram showing bit correspondence and address assignment of the image memory, and FIG. The figure shows a specific example of address allocation in Figure 9, and Figure 11 shows a specific example when the addresses in Figure 10 output from the CRT controller are actually given to memory banks 0 and 1. Figure 1
FIG. 2 is a diagram showing the relationship between the image memory explained in FIG. 9 and the screen on the CRT display. In the drawing, 1 is an image memory, 2 is a CRT controller, 3 is a CRT display device, 4 is a scanner, 6 is a control device, 11 is a memory array section, 14 is an input (write) data switching circuit, and 15 is an output (read) Data switching circuit, 16 is a bank 0 address selection circuit, 17 is a bank 1 address selection circuit, 21 is an address control circuit, 22 is a CRT address generation circuit, 25 is a display selection circuit, 23 is a read buffer for the control device,
24 indicates a CRT read buffer.

Claims (1)

[Scope of Claims] 1. An image memory control device comprising first and second memory devices for holding binary image information, wherein the information stored in the memory devices is Divide the bit string into even bit strings and odd bit strings, store the even bit strings and odd bit strings in one word in the first memory device and second memory device, respectively, and display them in their original density. An image memory control device characterized in that when an image is displayed, even-numbered bit strings and odd-numbered bit strings are alternately read out and displayed from both memory devices, and when displayed at 1/2 density, a bit string is read out and displayed from one memory device. . 2. In the image memory control device according to claim 1, the word numbers of the image memory composed of the first and second memories are assigned in the direction in which the bit strings are lined up, and the word numbers are assigned with address 0 as the base point. 1. An image memory control device characterized in that a 1/4 portion in the vertical and horizontal directions is addressed in the same manner as when no thinning is performed, thereby forming 1/2 thinned data in the vertical and horizontal directions.