JPH01184790A - Nonvolatile cam - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a nonvolatile CAM, and in particular, in addition to the normal memory function of reading and writing data by specifying an address, A non-volatile CAM (
Content-Addressable M
(emory).

[Prior art] Fig. 6 shows the l5SCC (Digest of Technique).
ical Papers pages 42-43 (19
1 is an electrical circuit diagram showing a conventional volatile CAM shown in 1985)).

In Figure 6, CAM is CMOS static RAM.
It consists of a section 1 and a match detection section 2. The coincidence detection section 2 consists of four MOS) transistors 3 to 6,
OS) Transistors 3 and 4 are connected in series, and MOS transistors 5 and 6 are connected in series. The source of the MOS) transistor 3 is grounded, the gate is connected to the second storage node N2 of the CMOS static RAM section 1 consisting of a flip-flop, and the gate of the MOS) transistor 4 is connected to the bit line BL forming the bit line pair. The drain is connected to the coincidence detection line M.

The source of MOS transistor 5 is grounded, and the gate is connected to C
First storage node N1 of MOS static RAM section 1
The gate of the MoS transistor 6 is connected to the bit line BL, and the drain is connected to the coincidence detection line M.

The CMOS static RAM section 1 is constituted by four MOS transistors 7 to 10, and includes MOS transistors 12 and 13 serving as two transfer gates. The source of the MOS transistor 12 is connected to the first storage node N1 of the CMOS static RAM section 1, the drain is connected to the bit line BL, and the gate is connected to the word line W. Also, CMOS static R
The source of the MOS transistor 13 is connected to the second storage node N2 of the AM section 1, the drain is connected to the bit line BL, and the gate is connected to the word! ! Connected to iIW.

Next, the operation of the conventional CAM shown in FIG. 6 will be explained. First, when performing a match search, all word lines W are set to "L# level" and match detection line M is set to "H" level.
This is performed by precharging the search data to a high level, applying search data to the bit line BL, and applying an inverted signal of the search data to the bit line BL. For example, when it is desired to search for "1", bit line BL is set to "H" level and bit line BL is set to "L" level.

When "1" is stored in the CMOS static RAM section 1, that is, when the first storage node N1 is at "H2" and the second storage node N2 is at "L" level, the MOS transistor 4 and 5 are conductive, but
Since the MOS transistors 3.6 are non-conductive, the coincidence detection line M is kept at the 'H' level.If '01 is stored in the CMOS static RAM section 1, that is, the first storage node If N1 is at “L” level and second storage node N2 is at “H” level, MO
The S transistors 3 and 4 become conductive, and the coincidence detection line M is discharged to the ground potential.

[Problem to be Solved by the Invention] As mentioned above, the conventional CAM is composed of the CMOS static RAM section 1 consisting of a flip-flop and the coincidence detection section 2. Therefore, when the power is turned off, the CMOS
There was a drawback that the data stored in the static RAM section 1 would be erased.

Therefore, the main object of the present invention is to provide a non-volatile CAM in which data does not disappear even when the power is turned off.

[Means for Solving the Problems] The present invention includes a plurality of memory cells arranged in a matrix of rows and columns, each having first and second storage nodes, storing information, and each column having a plurality of memory cells. a plurality of word lines for selecting memory cells to be aligned in a direction;
It includes a plurality of bit line pairs connected to memory cells aligned in the column direction, and a coincidence detection line that outputs a coincidence signal when information on the bit line pairs and information stored in the memory cells match. a non-volatile CAM with a gate connected to a first storage node of a memory cell, a first conduction terminal connected to one of a bit line pair, and a second conduction terminal connected to a match detection line. a first MOS transistor whose gate is connected to a second storage node of the memory cell, whose first conduction terminal is connected to the other of the bit line pair, and whose second conduction terminal is connected to the coincidence detection line; 2 MOS) transistors, and the memory cells are constituted by non-volatile memory.

[Operation] Since the memory cells of the nonvolatile CAM according to the present invention are composed of nonvolatile memory, there is no risk that the data stored up to that point will be erased even if the power is turned off.

[Embodiment] FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. First, the configuration of an embodiment of the present invention will be described with reference to FIG. NVRAM1l is a nonvolatile memory and includes first and second storage nodes Nl and N2. The gate of a first MOS transistor 14 is connected to the first storage node N1, and the drain is connected to the bit line BL.
, and its source is connected to a match detection line M. Second
The storage node N2 includes a second MOS transistor 15
The gate is connected, the drain is connected to the bit line BL, and the source is connected to the match detection line M. Further, the source of the third MOS transistor 12 is connected to the first storage node N1, the gate is connected to the word line W, and the drain is connected to the bit line BL. second storage node N
The source of the fourth MOS transistor 13 is connected to 2, the gate is connected to the word line W, and the drain is connected to the bit line BL.

The operation of the nonvolatile CAM shown in FIG. 1 is the same as the conventional example shown in FIG. 6 described above.

That is, the word line W is set to the "L" level, the match detection line M is precharged to the "H" level, a search data signal is applied to the bit line BL, and an inverted signal of the search data is applied to the bit line BL. Given.

If the information stored in NVRAMI 1 matches the search data, the match detection line M maintains the H level, and if they do not match, it is discharged and goes to the L level.

FIG. 2 is a block diagram showing the configuration of another embodiment of the invention. In the embodiment shown in FIG. 2, a MOS transistor 16 is connected in series to the MOS transistor 14 shown in FIG. 1, and a MOS transistor 17 is connected in series to the MOS transistor 15. More specifically, the gate of MOS transistor 14 is connected to second storage node N2, and the source is grounded. The drain of the MOS transistor 14 is connected to the source of the MOS transistor 16, the gate of the MOS transistor 16 is connected to the bit line BL, and the drain is connected to the match detection line M. In addition, MOS transistor 1
The gate of No. 5 is connected to the first storage node N1, and the source is grounded.

The drain of the MOS transistor 15 is connected to the source of the MOS transistor 17, the gate is connected to the bit line BL, and the drain is connected to the match detection line M. Even if the nonvolatile CAM is configured in this way, it can operate in the same manner as in FIG. 1 described above.

FIG. 3 is a more specific electrical circuit diagram of the nonvolatile CAM shown in FIG. 1. In FIG. 3, NvRAMll is composed of a static RAM 20 and an EEPROM 23, and information storage and reading operations are performed using a static RAM 20 and an EEPROM 23.
When it is carried out at AM20 and non-volatile memory is required,
The data stored in the static RAM 20 is
Transferred to OM23.

To explain the more specific configuration, static R
AM20 is composed of N-channel depletion type MO8) transistors 26 and 27 and N-channel enhanced type MO3) transistors 18 and 19. A power supply voltage is applied as a first reference potential to the drain of the N-channel depletion type MOS transistor 26, and the gate and source are connected to the first storage node N1. A power supply voltage is applied to the drain of the N-channel depletion type MOS transistor 27, and the gate and source are connected to the second storage node N2. The gate of the N-channel MOS transistor 18 is connected to the second storage node N2, the drain is connected to the first storage node N1, and the source is connected to the second storage node N2.
connected to the ground potential, which is the reference potential of the , the gate of the N-channel MOS transistor 19 is connected to the first storage node N
1, its drain is connected to the second storage node N2, and its source is grounded.

Furthermore, N channel MOS transistors 12 to 15
is provided, and an N-channel MOS transistor 12
has a gate connected to the word line W, a drain connected to the bit line BL, and a source connected to the first storage node N1. N-channel MOS transistor 13 has a gate connected to word line W, a drain connected to bit line BL, and a source connected to second storage node N2. N
Channel MOS transistor 14 has a gate connected to first storage node N1, a drain connected to bit line BL, and a source connected to match detection line M. The gate of the N-channel MOS transistor 15 is connected to the second storage node N.
2, its drain is connected to the bit line BL, and its source is connected to the match detection line M.

EEPROM 23 is an N-channel MOS transistor 21
．． 24 and a memory transistor 22. A clock signal CLK is applied to the gate of the N-channel MOS transistor 21, the source is connected to the second storage node N2, and the drain is connected to the source of the memory transistor 22. A program signal PRO is applied to the gate of the memory transistor 22, and the drain is connected to the source of an N-channel MOS transistor 24.

A clear signal CLR is applied to the drain and gate of the N-channel MOS transistor 24.

Next, the specific operation of the embodiment shown in FIG. 3 will be explained. First, when data is to be transferred, the clock signal CLK is set to the 'L' level, the program signal PRO is set to the 'L' level, and a high voltage pulse is applied as the clear signal CLR to the drain and gate of the N-channel MOS transistor 24. The data stored in the EEFROM 23 is erased. That is, the EEPR
The electrons accumulated in the floating gate of the memory transistor 22 of the OM 23 are extracted, and the threshold value is lowered.

Next, the clock signal CLK is set to "H" level,
Clear signal CLR is set to "L" level, and a high voltage pulse is applied to the gate of memory transistor 22 as program signal PRO.

If "1" is stored in the static RAM 20, the first storage node N1 is at the "H" level and the second storage node N2 is at the "L" level, so that the drain of the memory transistor 22 is grounded. potential, and electrons are injected into the floating gate.

If “Om” is stored in the static RAM 20, the first storage node N1 is at the “L” level, and the second storage node N2 is at the “H” level, the voltage at the drain of the memory transistor 22 is high. Therefore, electrons are not injected into the floating gate.In other words, since the potential difference between the gate and drain of the memory transistor 22 is small, electrons are accumulated in the floating gate.
There is no change in the electric charge that is present. In this way, data is transferred from the static RAM 20 to the EEPROM 23.

Next, data is transferred from the EEFROM 23 to the static RAM 20 using the clock signal CLK.

Program signal PRO and clear signal CLR are “H”
The level is set and the power supplied to NVRAM11 is turned off.
This is done by gradually increasing the voltage from V. At this time, if the threshold value of the EEPROM 23 is low, the second storage node N2 is charged and the static RAM 23 is charged.
0 is set to "0". On the other hand, EEFROM23
If the threshold value is high, the first storage node N1
The static RAM 20 is configured so that the signal is charged and becomes the "H" level, and "1" is set.

FIG. 4 is an electrical circuit diagram of another embodiment of the invention. In the embodiment shown in FIG. 4, the static RAM 20 and EEPROM 23 are constructed in the same manner as in the embodiment shown in FIG. 3 described above. The first storage node N1 has a MOS
The gate of transistor 17 is connected, the drain of MOS transistor 17 is connected to coincidence detection line M, and the drain is connected to the source of MOS transistor 15. The gate of this MOS transistor 15 is connected to the bit line BL, and the drain is grounded. Further, the gate of a MOS transistor 16 is connected to the second storage node N2, the source of the MOS transistor 16 is connected to the coincidence detection line M, and the drain is connected to the source of the MOS transistor 14. The gate of MOS transistor 14 is connected to bit line BL, and the source is grounded.

By configuring the non-volatile CAM in this manner, normal data storage is performed in the static RAM 20, and when non-volatile storage is required, it is stored in the static RAM 20, similar to the embodiment shown in FIG. The stored data can be transferred to the EEPROM 23. 'FIG. 5 is an electrical circuit diagram showing another embodiment of the present invention. In this embodiment, sensor lines S and S are newly provided to provide data to be searched. The gate of a MOS transistor 14 is connected to the first storage node N1, and the sensor line S is connected to the drain. The source of the MOS transistor 14 is M
OS) connected to the gate of the transistor 25. The gate of the MOS transistor 15 is connected to the second storage node N2, the drain is connected to the sensor line S, and the source is connected to the gate of the MOS transistor 25. M.O.S.
The drain of the transistor 25 is connected to the coincidence detection line M, and the source is grounded.

When searching for data in this embodiment, word Hw is set to "L" level and match detection line M is set to "H" level.
This is performed by precharging the search data to the level, applying an inverted signal of the search data to the sensor line 100, and applying a search signal to the search line S.

For example, when it is desired to search for "1", the sensor line S is set to the 'L2 level, and the sensor line S is set to the "H" level. If "1" is stored in the static RAM 20, the first storage node N1 is at the "H" level, and the second storage node N2 is at the "L" level, the MOS transistor 14 becomes conductive. , the gate potential of the MOS transistor 25 becomes "L2 level", and the MOS transistor 25 becomes non-conductive, so the coincidence detection line M becomes -
Maintain the “H” level.If the static RAM20
0” is stored, and the first storage node N1 is “L”
level, and if the second storage node N2 is at the 'H' level, the MOS transistors 15 and 2
5 becomes conductive, and the coincidence detection line M becomes the ground potential.

[Effects of the Invention] As described above, according to the present invention, by configuring the memory cells with non-volatile memory, there is no fear that data will be erased even if the power is cut off.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of another embodiment of the invention. Figure 3 shows the non-volatile CAM shown in Figure 1.
It is a specific electric circuit diagram of. FIG. 4 is an electrical circuit diagram of another embodiment of the invention. FIG. 5 is an electrical circuit diagram showing another embodiment of the present invention. Figure 6 shows conventional CA
FIG. 2 is an electric circuit diagram showing the configuration of M. Figure Nioite, 11+iNVRAM, 12 to 17.2
1.24.25 is an N-channel MOS transistor, 18
．． 19 is an N-channel enhanced type MOS transistor, and 20 is a static RAM. 22 is a memory transistor, and 23 is an EEPROM. 26 and 27 indicate N-channel depletion type MOS transistors.

Claims (1)

[Scope of Claims] A plurality of memory cells arranged in a matrix of rows and columns, each having first and second storage nodes, for storing information, and each memory cell arranged in the column direction. a plurality of word lines for selecting memory cells to be stored, a plurality of bit line pairs connected to the memory cells aligned in the column direction, information on the bit line pairs and information stored in the memory cells; a match detection line that outputs a match signal when the numbers match, the non-volatile CAM includes a gate and first and second conduction terminals, the gate is connected to the first storage of the memory cell. node, the first conduction terminal is connected to one of the bit line pair, and the second conduction terminal is connected to a first MOS transistor connected to the coincidence detection line, and a gate and a first and second MOS transistor. 2 conduction terminals, the gate is connected to a second storage node of the memory cell, the first conduction terminal is connected to the other of the bit line pair, and the second conduction terminal is connected to the match detection terminal. a second MOS transistor connected to a line, the memory cell being constituted by a non-volatile memory;
Non-volatile CAM.