JPH01185933A - Testing of semiconductor wafer - Google Patents

Abstract

PURPOSE:To reduce the ratio of a dedicated area occupied by a ring oscillator on a semiconductor water by a method wherein a smallscale inverter circuit row is formed inside a semiconductor chip apart from a functional circuit, two or more circuit rows are connected longitudinally by using a probe card in order to constitute the ring oscillator and an oscillation frequency is measured. CONSTITUTION:In addition to functional circuits 12, an inverter circuit row 7 is formed inside individual semiconductor chips 13 on a semiconductor wafer. Inverter rows 7-1 and 7-2 are connected by using a wiring part 3-1; inverter rows 7-2 and 7-3 are connected by using a wiring part 3-2; an output of the inverter row 7-3 is returned to an input of the inverter row 7-1 by using a wiring part 3-3; at the same time, an output terminal 4 is taken out. wiring parts 3-4, 3-5 are used to apply a power supply and a ground to the inverter circuit rows 7-1-7-3. Prior to P/W of the functional circuits 12, a probe card 1 is aligned with a ring oscillator row; the output terminal 4 of the probe card 1 is connected to a frequency counter; a frequency is measured. By this setup, the ratio occupied by a ring oscillator chip is reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for testing the operating speed of an integrated circuit formed on a semiconductor wafer using a ring oscillator, and in particular to a method for testing the operating speed of an integrated circuit formed on a semiconductor wafer using a ring oscillator. Regarding improvement of the ratio of exclusive area.

[Conventional technology]

As shown in the circuit diagram of FIG. 4, a ring oscillator is constructed by cascading an odd number of inverter circuits 17 in series and feeding back the output of the final stage to the input of the first stage. When the delay time per inverter stage is tPD; the number of stages is n, the ring oscillator oscillates at a certain frequency. In other words, even if the speed of an inverted inverter is high, if the number of stages n is large, the oscillation frequency will be lower, so if this ring oscillator is provided on a part of the semiconductor wafer, the performance (speed) of the high-speed semiconductor integrated circuit can be improved. It is possible to test with a low-speed tester. In other words, by measuring the low-frequency oscillation frequency of the ring oscillator, it is possible to test the true speed of a high-speed semiconductor integrated circuit. If high-speed testing is not possible due to cost reasons, it is very effective to provide this ring oscillator on a part of the semiconductor wafer to guarantee the performance of the semiconductor wafer on a wafer-by-wafer basis. be.

FIG. 5 shows a conceptual diagram of a conventional semiconductor wafer testing method.

In this figure, each semiconductor chip 13 includes a ring oscillator 18 as well as its ground and power source.

A method of providing and arranging output pads 9, 10, and 11 is used.

The test procedure is that before running the functional circuit 120P/W, the dedicated probe card 1 is aligned with the ring oscillator circuit 18 at an appropriate position, the probe 2 is grounded, and each pad 9, 10 . 11 and connect a frequency counter (not shown) to the output terminal 4 through the wiring 3.
The oscillation frequency of the ring oscillator 18 is measured, and if there is no speed problem, the functional circuit 120P/W is performed.

By using the method described above, it is possible to check the speed of semiconductor wafers and send only wafers without problems to the subsequent process, thereby improving the assembly yield.

FIG. 6 shows another conventional example, in which a ring oscillator chip 19 is made independently and combined with a functional chip 20 for imposition (minimum unit of repeated arrangement). . In the figure, for example, a ring oscillator chip 19-1 and a functional chip 7 are shown.
“20-1.

20-2.20-3 constitutes imposition. The test procedure is the same as that of the conventional example shown in FIG. 5, so a description thereof will be omitted.

[Problem that the invention seeks to solve]

In the conventional example shown in FIG. 5 described above, the ring oscillator 18, which is not intended for the purpose, is arranged in each chip 13, which increases the chip size and has the disadvantage of being inefficient in terms of area. .

Furthermore, in the conventional example shown in FIG. 6 described above, the functional chips 20 cannot be placed in one quarter of the area of the semiconductor wafer, which is still inefficient.

Of course, with imposition, it is possible to increase the number of chips and reduce the proportion occupied by the ring oscillator chip 19, but since there is a natural limit to the size of imposition, especially when the chip size is large, it is inevitable to use functional chips. The relative ratio of the area occupied by the ring oscillator chip to the area occupied by the ring oscillator chip increases. Conversely, if the chip size is small, the ring oscillator 19 itself may not fit inside.

Furthermore, in the conventional example shown in FIG. 6, there is no need to assemble the ring oscillator chip 19, so once the speed test of the ring oscillator is completed, there is no need to separate it from the functional chips, which is a cumbersome process. is necessary.

[Means for solving problems]

In the semiconductor wafer testing method of the present invention, semiconductor chips having an inverter circuit array in which a plurality of inverter circuits are cascaded in addition to functional circuits are arranged on a semiconductor wafer, and the inverter circuit array in the semiconductor chip is detected using a probe card. A plurality of ring oscillators are connected in series to form a ring oscillator, and the speed of semiconductor wafers is tested by measuring the oscillation frequency of the ring oscillator.

〔Example〕

Next, the present invention will be explained in more detail with reference to the drawings.

FIGS. 1 and 2 are conceptual diagrams of a semiconductor wafer testing method according to an embodiment of the present invention. In addition to the functional circuit 12 (main circuit), each semiconductor chip 13 on the semiconductor wafer has an inverter circuit array 7 whose contents are shown in FIG. 2 (of course, the inverter circuit array is (The number of stages is not limited to three as shown in FIG. 2, but any number of stages may be used.)

Each inverter circuit array 7 has an input pad 8°, a ground pad 9. Power pad 10. It is connected to the output pad 11.

The probe card 1 has three inverter circuit arrays 7-1. 7-2. 7-3 is connected to form a ring oscillator.

That is, the wiring 3-1 connects the inverter rows 7-1 and 7-2.
The wiring 3-2 connects the inverter rows 7-2 and 7-3, and the wiring 3-3 returns the output of the inverter row 7-3 to the input of the inverter row 7-1, and simultaneously takes out the output terminal 4.

Further, the wirings 3-4, 3-5 respectively provide power and ground to the inverter circuit array 7-1.7-2.7-3.

Prior to the functional circuit 120P/W, the probe card 1 is aligned with the ring oscillator row at an appropriate position, the output terminal 4 of the probe card 1 is connected to a frequency counter, the frequency is measured, and semiconductor wafers are sorted. In addition, power terminal 5
．． An operating voltage is applied from the ground terminal 6.

FIG. 3 is a conceptual diagram of another embodiment of the semiconductor wafer testing method according to the present invention. In this figure, the wires 3-1.3-2.3-3 in FIG. 1 are printed wires 21-1.21-2.21-3 on each probe card. The other contents are the same as the explanation regarding FIG. 1.

〔Effect of the invention〕

As is clear from the above explanation, in the semiconductor testing method according to the present invention, a relatively small-scale inverter circuit array is arranged inside the semiconductor chip separately from the functional circuits, and a suitable plurality of these inverter circuits are By using a method in which a ring oscillator is connected in series using probe cards and its oscillation frequency is measured, the ratio of the area occupied by the ring oscillator on the semiconductor wafer is reduced and functional chips can be placed efficiently. In addition, when the ring oscillator chip is placed independently from the functional chip, marking the ring oscillator chip that is no longer needed after the speed test is completed.
This has the effect of eliminating the extra work of separating it from the necessary functional chips.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of a semiconductor wafer testing method according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of an inverter circuit array, and FIG. 3 is a conceptual diagram of a test method according to another embodiment of the present invention. Conceptual diagram, Figure 4 is a circuit diagram showing an example of a ring oscillator, Figure 5 is a conceptual diagram showing a conventional semiconductor wafer testing method, and Figure 6 is a plan view showing an example of a method for mounting ring oscillator chips. It is. 1... Probe car V, 2... Probe,
3... Wiring, 4... Output terminal, 5...
...Power terminal, 6...Ground terminal, 7...
... Inverter circuit row, 8 ... Input pad,
9... Ground pad, 10... Power supply pad, 11... Output pad, 12... Functional circuit, 13... Semiconductor chip, 14...
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Claims (1)

[Claims] In addition to functional circuits, a semiconductor chip having an inverter circuit array in which a plurality of inverter circuits are cascaded is arranged on a semiconductor wafer, and a plurality of inverter circuit arrays in the semiconductor chip are cascaded using a probe card to create a ring oscillator. 1. A semiconductor wafer testing method comprising: a ring oscillator; and a speed test of a semiconductor wafer is performed by measuring the oscillation frequency of the ring oscillator.