JPS6331131A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To improve the chip numbers per wafer while relieving the load on transmitting test signals for outer tester and shortening the die sort testing hours by a method wherein a die sort test circuit part is formed in the region excluding respective chip regions for manufacturing integrated circuit patterns. CONSTITUTION:A die sort test circuit part 3 to perform the die sort test by impressing die sort test signals on one or multiple chip regions for manufacturing respectively formed integrated circuit patterns is formed on a region of a wafer excluding respective chip regions 1. In order to perform the die sort testing, a pointer of probe card of an outer tester is applied to a power supply pad of a chip circuit of the chip regions 1 for testing an input pad, output pad of the test circuit 3 to activate a chip circuit as well as the test circuit. Through these procedures, either one or multiple chip regions 1 can be tested simultaneously while contracting the chip size and increasing the chip numbers per wafer.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a semiconductor wafer on which a circuit pattern to be tested is formed in a die sorting process when manufacturing semiconductor integrated circuits. , particularly regarding chip test circuitry on wafers.

(Prior Art) In the die sorting process when manufacturing semiconductor integrated circuits, each chip circuit is tested on a semiconductor wafer 30 in which circuits and ramie turns are formed in each of a large number of chip areas 31, as shown in FIG. Do the following. Conventionally, there have been cases in which a test circuit for the die sort test is provided in each chip area, and cases in which it is not provided in each chip area. That is, for example, for a microprocessor chip IC as shown in FIG.
A test circuit is provided in addition to the M, RAM, and random logic sections (arithmetic circuits, registers, etc.), and during the die sort test, the external test circuit is By applying a startup signal from the test device, the test circuit on the chip is activated to generate a test signal, and the output signal of the chip circuit is compared with the expected test output signal (theoretical value) to determine pass/fail. That's what I was doing. In addition, for the Noah Dart chip 51 as shown in FIG.
A test signal is applied from an external test device to the output terminal 53, and the output signal of the output terminal 53 is compared with the test expected value signal to determine the quality.

However, as mentioned above, wafers with test circuits inside each chip can simplify the test signal (pattern signal) generation circuit of external test equipment, but the chip size is large due to the test circuit, and The number of chips will decrease. In addition, if a test circuit is provided inside the chip, this test circuit is not necessary for the user, but the state after the chip is divided (productized as an integrated circuit)
There is a risk that the user may accidentally activate the test circuit, which may raise unnecessary questions for the user.
There is a risk that this will lead to time loss. on the other hand,
As mentioned above, for wafers that have a group of chips to which test signals are applied from an external test device, it is necessary to provide the external test device with a circuit for generating test signals (pattern signals), which places a heavy burden on the external test device. Become. Also,
The conventional wafer described above needs to be modified so that the needle of the glove card touches the chip to be tested each time each chip is tested), and this is necessary to move the needle and input the test signal for each chip. There was a problem in that the test took a long time.

(Problems to be Solved by the Invention) As described above, the present invention is applicable to cases in which a die sort test circuit is provided inside each chip, and when a die sort test circuit is not provided inside each chip, a test signal is sent to a chip from an external test device. It was designed to solve all of the problems that arise when applying voltage to external test equipment. It is an object of the present invention to provide a semiconductor wafer that can reduce the amount of time required for a die sort test, reduce the die sort test time, and eliminate the possibility of a user starting up a die sort test circuit after chip division.

[Structure of the Invention] (Means for Solving the Problems) The semiconductor wafer of the present invention is characterized in that a strike signal is applied to one or more of the chip areas on which integrated circuit patterns are formed and which are not intended for commercialization by die sorting. A die sort test circuit section for performing a die sort test by applying an electric current is formed in a region on the wafer other than each chip region for commercialization.

(Function) During the die sort test, the needle of the glove card of the external test device is applied to the input pad and output pad of the test circuit section, and the test circuit section is activated, thereby dividing the chip area for commercialization one by one. Or you can test multiple items at the same time. Therefore, it is not necessary to use a die sort test circuit for each chip area for commercialization, and it is possible to reduce the chip size and increase the number of chips per chip. The burden for signal generation can be reduced. Further, by configuring the device to test a plurality of chip areas for commercialization simultaneously or sequentially without moving the needle of the glove card, the test time can be shortened.

Moreover, since each chip area for commercialization does not include a die sort test circuit after chip division, there is no possibility that the user will accidentally activate the die sort test circuit section.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a portion of a semiconductor wafer on which integrated circuits/four turns have been formed, and shows the arrangement relationship between the chip area and the test circuit forming area.

That is, 1... is a chip area for commercialization, and each chip does not include a test circuit for a die sort test (die sort test circuit). and,
A die sort test circuit section 3 for die sort testing is applied to the chip dividing area (dicing line area) 2 between the chip areas (this is done by applying the needle of the probe card of an external test device to the die sort test circuit section 3). Input pad for applying signals to start the test circuit,
and an output/flat for checking the output from the chip circuit, as well as wiring for connecting these and the circuit in the chip area 1). In this case, the wiring between the circuit in the chip area 1 and the test circuit section 3 may be routed through the pad 1' within the chip area 1, or may be routed directly without passing through the pad within the chip. Further, a test circuit power supply or rad may be provided in the test circuit section 3, or the power supply wiring of the chip circuit may be extended and wired to the test circuit. In addition, the test circuit section 3
Although it may be formed corresponding to each chip area 1,
Multiple pieces (4 pieces in this example) to improve test efficiency.
A selection circuit is provided in the dicing line area 2 corresponding to each of the four chip areas 1, and is capable of selectively transmitting and receiving test input signals and test output signals to and from the four chip areas 1. By doing so, it is possible to reduce the number of arms of the test circuit section 3. Further, test input signals are simultaneously applied from the test circuit unit 3 to the four chip regions 1, and each test output signal is formed to be derived to a separate test output signal pad. may be tested simultaneously.

According to the semiconductor wafer of the above embodiment, during a die sort test, probes of an external test device are connected to the input pad, the output/4' node of the test circuit section 3, and the power supply/2 node of the chip circuit of the chip area 1 to be tested. By applying the needle to the card, activating the chip circuit, and activating the test circuit, the chip areas 1 can be tested one by one or a plurality of chip areas at the same time. Therefore, each chip area 1 for commercialization does not need to have a built-in die sort test circuit, and it is possible to reduce the chip size and increase the number of chips per wafer. It is possible to reduce the burden caused by the outbreak. Further, by testing a plurality of chip areas 1 for commercialization simultaneously or sequentially without moving the position of the needle of the probe card, the test time can be shortened. Furthermore, since each chip area 1 for commercialization does not include a die sort test circuit after chip division, there is no room for the user to accidentally activate the die sort test circuit.

Note that the present invention is not limited to the above-mentioned embodiments, and the specific configuration of the Dyne-6 tochist circuit section can be modified in various ways, and its position on the wafer may be anywhere outside the chip area for commercialization. As in the wafer shown in the M2 diagram, a die sort test circuit part chip area 21 having the same size as the chip area l for commercialization may be provided. In this case, the die sort test circuit section chip area 2
Wiring is performed so that eight chip areas 1 around the test circuit section 1 are tested. According to such a wafer, substantially the same effects as those of the above-mentioned embodiments can be obtained, and the space of the die sort test circuit section becomes wider, so that the /'P-turn design thereof becomes easier.

[Effects of the Invention] As described above, according to the semiconductor wafer of the present invention, the die sort test circuit section is formed in an area other than each chip area for commercialization on the wafer, so that it is possible to reduce the chip size. We aim to increase the number of chips in the chip, reduce the burden on external test equipment to generate test signals, shorten die sort test time, and prevent users from incorrectly checking the die sort test circuit section after chip division. Effects such as eliminating the room for activation can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing the planar arrangement of circuits and turns by taking out a part of a semiconductor wafer according to an embodiment of the present invention, and FIG. 2 is a diagram showing a semiconductor wafer according to another embodiment of the present invention. Figure 3 is a plan view schematically showing a conventional semiconductor wafer, and Figure 4 is a semiconductor chip with a die sort test circuit. FIG. 5 is a diagram illustrating a circuit configuration on a chip in an example of a semiconductor chip that does not have a conventional die sort test circuit. 1... Chip area for commercialization, 2... Dicing line area, 3... Die sort test circuit section, 2... Chip area for die sort test circuit section. Applicant's agent Takehiko Suzue

Claims (1)

[Claims] A die sort test circuit section for performing a die sort test by applying a die sort test signal to one or more of the chip areas for commercialization in which integrated circuit patterns are formed is provided in the above commercial product. A semiconductor wafer characterized in that the semiconductor wafer is formed in a region on the wafer other than each chip region.