JPH0118623B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a halftone processing device that performs halftone processing on an image signal.

Projecting an image onto a photoelectric conversion element such as a CCD and converting the video signal, which is the output signal of the photoelectric conversion element, into a digital signal is widely used in facsimiles and other devices. Attempts have been made to construct a copying machine using a laser beam printer that employs this method.

In this case, when the video signal changes from a white signal to a black signal or from a black signal to a white signal, the signal in the changing part is unclear, and when the obtained signal is reproduced to obtain an image, thin lines and white parts appear. There is a problem that the boundary between the black part and the black part tends to be unclear.

This is due to slight image blur caused by the optical system and slight deterioration in the video signal transmission system.

Therefore, attempts have been made to enhance the thin lines and the boundaries by adding processing to the video signal, but no satisfactory results have been obtained.

The present invention was proposed in view of the above points, and
An object of the present invention is to provide a halftone processing device that can clearly reproduce thin lines and boundaries when performing halftone processing on a video signal.

That is, the present invention provides a video input means for inputting a video signal, a clock input means for inputting a clock synchronized with the video signal, and a clock input by the clock input means for the input video signal input by the video input means. a means for performing halftone processing using the input video signal, the halftone processing means requiring a first processing time for the halftone processing; a means for performing boundary processing on a boundary portion of the input video signal, the means for performing a boundary Boundary processing means whose processing requires a second processing time; means for adjusting the time difference between the first processing time and the second processing time, the adjustment means adjusting the time difference using the clock; and The halftone processing device comprises a synthesizing means for synthesizing the output signals of the two processing means whose time is adjusted by the adjusting means.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment embodying the present invention, in which a video signal is input to a first binarization circuit 1 using a known AD converter, etc., and is directly binarized. A first binarized signal is obtained. At the same time, the video signal is input to a known differentiation circuit 2 for differentiation, and the differentiated signal is rectified by an absolute value circuit 3 and then input to a second binarization circuit 4 using a known AD converter. By valuing the second
A binary signal is obtained. The first and second binarized signals are input to the synthesis circuit 5, where they are synthesized, and finally a binarized signal of the image signal is obtained.

FIG. 2 shows various signal waveforms in the above case, where a represents the video signal and the dotted line represents the threshold level of the first binarization circuit 1. In FIG. b is the first
The binary signal c is a differential signal, and the dotted line is a signal obtained by rectifying the differential signal. d is a second binarized signal obtained by binarizing the rectified differential signal. e
is the final binarized signal of the image signal obtained by combining the first and second binarized signals b and d.

FIG. 3 shows an example of an electric circuit based on FIG. 1, in which the first binarization circuit 1 uses a dither method. The AD converter 6 includes a sample and hold circuit and four comparators, and outputs the output signal of the comparator as it is in synchronization with the clock pulse. One of these four outputs is sequentially selected in response to a clock signal and a synchronization signal. What is the clock signal here?
This is a clock that outputs a video signal from a photoelectric conversion element such as a CCD, and a synchronization signal is a signal that is generated when scanning one line of an image is started.

A delay circuit 7 is provided between the first binarization circuit 1 and the synthesis circuit 5, and delays the first binarization signal. This is obtained after the second binary signal is differentiated by the differentiating circuit (analog) 2, so the second binary signal is delayed by the time constant of the differentiating circuit 2, so the delay is large. This is to correct the A shift register is used in the delay circuit 7 to delay the first binary signal. Note that the presence or absence of the delay circuit 7, the magnitude of the delay, etc. are appropriately determined depending on the individual circuit.

If the dither method is used in the first binarization circuit 1 as described above, a binarized signal can be obtained immediately, making it possible to record halftone images without reducing the pixel density of white and black areas. becomes. However, if there is image blurring in the optical system and deterioration of the video signal, the thin line and the boundary between the white part and the black part become unclear as described above.

In this embodiment, the dither method is used for the first binarization circuit 1 that directly binarizes the video signal, and the dither method is not used for the second binarization circuit 4, so that the thin lines and the above-mentioned boundaries are not sharpened. It can be binarized and clearly recorded on the outline of the halftone part.

FIG. 4 shows a second embodiment of the present invention, in which a differentiation circuit 8 is provided in place of the absolute value circuit 3.
The other components are the same as those in the example shown in FIG. 1, and the same parts are given the same reference numerals. However, when the waveform is differentiated twice, the waveform becomes as shown in FIG. 2(f). The dotted line is the level of the second binarization circuit 4, and when the level is below this level, the second binarization signal is output.

As described above, the present invention provides video input means for inputting a video signal (corresponding to the video signal input shown in FIG. 3 in the embodiment), and clock input means for inputting a clock synchronized with the video signal (corresponding to the video signal input shown in FIG. (corresponding to the clock shown in FIG. 3), means for performing halftone processing on the input video signal input by the video input means using the clock input by the clock input means; A halftone processing means (corresponding to the first binarization circuit 1 shown in FIG. 3 to which both a clock and a video signal are input in the embodiment) which requires a first processing time for processing, and a boundary of the input video signal. Boundary processing means that performs boundary processing on a portion and requires a second processing time (in the embodiment, the differentiating circuits 2 and 8
), means for adjusting the time difference between the first processing time and the second processing time, and adjusting means for adjusting the time difference using a clock synchronized with the input video signal (corresponding to the first processing time and the second processing time); A delay circuit 7) that delays the video signal from a photoelectric conversion element such as a CCD according to the clock shown in Figure 3;
and a synthesizing means (synthesizing circuit 5 in the embodiment) for synthesizing the output signals of the two processing means time-adjusted by the adjusting means, so that the halftone part of the image is reproduced as a halftone, and the halftone part of the image is A video signal that clearly reproduces contours can be obtained. In this case, each of the halftone processing and boundary processing requires a unique processing time (first and second processing time), and there is a difference between the two processing times. High-quality images can be obtained by adjusting and compensating, and since a clock synchronized with the input video signal is used to adjust the time difference, the time difference can be corrected with high precision.
Also, its configuration can be made simple.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 a to f are output waveform diagrams of various parts, FIG. 3 is an electric circuit diagram based on FIG. 1, and FIG. FIG. 2 is a block diagram of an embodiment. 1 is a first binarization circuit, 2 is a differentiation circuit, 3 is an absolute value circuit, 4 is a second binarization circuit, and 5 is a synthesis circuit.

Claims (1)

[Scope of Claims] 1. Video input means for inputting a video signal; clock input means for inputting a clock synchronized with the video signal; inputting the input video signal inputted by the video input means by the clock input means; means for performing halftone processing using a clock generated by the input video signal, the halftone processing means requiring a first processing time for the halftone processing; and means for performing boundary processing on a boundary portion of the input video signal; , a boundary processing means that requires a second processing time for the boundary processing; a means for adjusting a time difference between the first processing time and the second processing time, the adjustment adjusting the time difference using the clock; and a synthesizing means for synthesizing the output signals of the two processing means time-adjusted by the adjusting means.