JPH01187655A - Memory check system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a memory checking method particularly suitable for personal computers and workstation memory systems.

[Conventional technology]

The capacity of information devices such as personal combinators is increasing year by year as memory elements become more highly integrated. Recently, the standard configuration is 1-2MB, and the maximum configuration is 8-8MB.
1 (SMB is common).

On the other hand, memory elements range from 64Kb to 256Kb, and recently IMb has become the standard, and it is predicted that 4Mb elements will become mainstream in the near future. Amid such increased integration, memory devices are required to have higher reliability than ever before.

Memory failures can be roughly divided into two types: one is a hardware failure (hereinafter abbreviated as hard error), and the other is a soft error caused by alpha rays. Causes of hard errors include pinholes in the oxide film, interlayer defects caused by foreign substances, photoresist defects, metallization defects, and element destruction, and the error rate is approximately 20 to 50 FIT (I FT
T is the probability that a failure will occur once every 10 hours), and it has been reported that failures occur in the market. (“Hitachi IC Memory Data Book” published by Hitachi, Ltd. (1988)
In order to detect such memory hardware failures, it is common for personal combinators to perform a memory check when the power is turned on.

Figure 3 is a block diagram of the parts related to the memory buttons of a personal computer, where 1 is the CPU, 2 is the address bus of CPU 1, 3 is the same (data bus of CPU 1, 4 is the memo 9. 5 is the program at startup) RO where is stored
It is M. Further, 6 is a memo 9 read signal, and 7 is a memory write signal.

After the power is turned on, the CPU 1 starts distributing instructions from a specific address in the ROM 5. After passing through some initial settings, the memory check program is executed. Figure 4 is an example of the memory check program. Now, the memo 94 is located at addresses 000000H to 3F F'FFF.
Assume that there is aMf3 of H (H is an abbreviation for HEX and represents a hexadecimal number). The program writes arbitrary data one byte at a time from address 000000H to the memory 4 using the memo 9 write signal 7 (112), and then the data 1 (113) output by the memory read signal 6 is equal to the write data. - is checked (114). And the final address of memory 4 is 3F FFFP H4
When C is reached, the memory check ends (11 (5)).

Furthermore, there are cases where two or three types of access data are prepared and the flow shown in FIG. 4 is repeated.

[Problem to be solved by the invention]

In the memory check described above, for example, once memory 4
Assuming that it takes 500 rS to access, 4194304 (
= 4M) x 500 x 2 + 42 seconds, and the memory check takes several tens of seconds due to the execution time of the memory check program itself and the time for multiple loops when the access data is changed.

Furthermore, the control flow shown in FIG. 4 has a low ability to detect address failures. For example, if &'4000003H is accessed to 000002)1 due to a failure, it cannot be detected because it is simply written, read and compared. An example of a memory check address pattern for determining such problems is the marching pattern test method.

FIG. 5 shows an example of this control flow, in which five memory accesses are required to test a certain bit of a certain address (117, 120, 122, 126, 128). In the case of 8 pits, if the capacity of memory 4 is 4MB, 4
194304 x 500 x 4 x 8 = 67
A memory access time of several seconds is required. Of course, we also have to add the program execution time, so the actual memory check will take several minutes.

However, users of personal combiators and the like have a strong desire to use the devices as soon as the power is turned on, and there are strong complaints that the time required for initial settings and memory checks should be shortened as much as possible.

As one method to solve this problem, JP-A No. 62-49
Publication No. 427 describes a method in which only the minimum necessary address range of memory 4 is checked when the power is turned on, and the rest is performed while waiting for user input after the system has started up. It is being in this way,
Although the apparent system start-up time is reduced, it does not provide a fundamental solution, as large programs cannot be executed until all memory checks are completed.

An object of the present invention is to provide a memory check method that reduces the time required for the memory check itself without compromising the reliability of the memory check.

[Means to solve the problem]

The purpose of the above is to ensure that the buttons of information devices such as personal combinators always have a battery-backed calendar timer circuit, and that failures of the memory element itself can occur within 20 to 50 seconds.
Focusing on the FIT and low FIT, based on information such as the date, day of the week, and time read from this calendar timer circuit, the method to check (-!147)7 reduces the dress range and the data to be tested. This is achieved by selecting bits to reduce the amount of checking on each rise.

[Effect]

The calendar timer, which maintains these days of the week, etc., is powered by a lithium battery, etc., and operates even when the power is turned off.
Data corresponding to the day of the week and month can be obtained by reading from the PU1.

For example, a method may be considered in which data bits to be checked are assigned to each day of the week, noting that actual business is generally carried out nine times from Monday to Friday. Monday is the beginning of the week so all bits, Tuesday is Pitlo 11
．． Bit 213 on Wednesday. Thursday (beep) 4,5. If bits are set to 6.7 on Fridays, each bit can be checked without missing a single bit on a weekly basis while doing daily work, and the time required to start each bit is 2 bits out of 8 bits. Since you only need to check the time, the time can be reduced to 1/4.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 2 shows an example of a hardware configuration, which is characterized by the addition of a calendar clock circuit 8 compared to FIG. 3, which shows a conventional example. Reference numeral 9 denotes an I for reading data from a calendar clock circuit which is a central device.
10 read signal is shown.

Reference numeral 10 denotes a battery for retaining the contents of the calendar clock circuit 8 and for continuing its operation when the power is turned off.

FIG. 1 is an example of a control flow of a program stored in the ROM 5 for implementing the memory check method of the present invention. First, the day of the week information is read from the calendar timer circuit 8 using the I10 read signal 9 (101
). This content is judged as 102 to 105 busy and the memory bit corresponding to each day of the week is checked (1
06-110). A marching pattern method as shown in FIG. 5 may be used to check the memory.

The present invention may have various other applications. First, taking as an example the HD146818 manufactured by Hitachi, which is a typical IC of the calendar timer circuit 8, it is possible to read out information such as the year, month, day, hour, minute, and second in addition to the day of the week. In addition to the simple write/continuous write method shown in Figure 4 and the marching pattern method shown in Figure JE5, memory checking methods include the checker-flag method, striped turn method, gear roping method, and forking method. Various types of address patterns are known, and various memory tests can be performed by combining them.

In addition, memo 94 the redundant bits such as parity and ECC.
The memory system added to the memory system may have a function to arbitrarily invert these redundant pits to generate a pseudo failure, but the contents of the calendar timer circuit 8 may determine which bits cause the failure and how. You may choose.

Another possible method is to perform a memory check only when the power is turned on for the first time in a day, and omit it from the second time onwards.

〔Effect of the invention〕

According to the present invention, there is an effect that the memory check can be significantly shortened without reducing the reliability of the memory check, and the user is not made to wait when the system is powered on.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing one embodiment of the present invention, and FIG.
Figure 3 is a block diagram showing an embodiment of the present invention, Figure 3 is a block diagram of a conventional example, Figure 4 is a flowchart of a memory check using simple writing/reading, and Figure 5 is a flowchart of a memory check using a marching pattern method. It is. 1...CPU, 2...Address bus, 3...Data bus, 4...Memory, 5...ROM, 6...Memory read signal, 7...Memo 9 write signal, 8... ...Calendar clock circuit, 9...El read signal, 1o.
··battery. Representative patent attorney Masaru Ogawa Male name 1st 2nd M 3rd 4th

Claims (1)

[Scope of Claims] 1. An information processing device comprising a CPU, a ROM storing a program executed by the CPU when power is turned on, a writable memory, and a calendar timer circuit whose contents are held by a battery, The program in the ROM reads the contents of the calendar timer circuit, and based on the contents, the program in the ROM selects a memory check method of the memory.
A memory check method characterized by executing