JPH01187943A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having dielectric isolation, junction leakage of which is reduced, through a simple method by filling a trench section to become a dielectric isolation region with an insulator at a temperature equal to or higher than a temperature at the time of impurity diffusion after the formation of dielectric isolation. CONSTITUTION:In a dielectric isolation process in which a trench section 5 formed to a semiconductor substrate is filled with an insulator 7, the trench section 5 is filled with the insulator 7 at a temperature equal to or higher than a temperature at the time of the thermal diffusion of an impurity in a postprocess. An n<+> type buried region 2, an n-type epitaxial layer 3 and a CVD- SiO2 film 4 are shaped to the p-type Si substrate 1, the SiO2 film 4 in a dielectric isolation region is removed, Si is etched to form the trench 5, and a channel stopper region 6 is shaped onto the bottom of the trench 5. The SiO2 film 7 is formed at a temperature of approximately 950 deg.C an the trench 5 is buried with the SiO2 film 7, the SiO2 film 7 is left only in the trench 5 and the surface is flattened, a filed SiO2 film 9 and an n<+> collector region 10 are shaped, and a p<+> type region 11 and an n<+> type emitter region 12 are formed at 950 deg.C or 900 deg.C.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that can form insulation isolation with little junction leakage.

2. Description of the Related Art Conventionally, an insulation isolation method has been proposed in which a CVD SLO2 film is buried in a trench.

Bipolar LSI using the manufacturing process of the above insulation isolation method
The case of manufacturing is shown in FIGS. 3A to 3F.

The p-type St substrate 1 has a diffusion depth of approximately 1 μm.
A +-shaped embedded region 2 is formed. Next, an n-type epitaquin layer 3 having a thickness of 111 m is formed. C with a thickness of approximately 1.2 μm
A VDSI02 film 4 is formed, and the CVD-8z O2 film 4 in the insulation isolation formation region is removed by photoetching (FIG. 3A).

Next, the exposed Si was etched using CV D S 102 [4 as an etching mask to a depth of about 2
, 5 to 3.571 m, and a groove 6 with a width of 1.27 zm is formed. Then, using the CVD S to 2 film 4 as a mask, poron ions are implanted into the bottom of the groove 5 (channels).
A collar region 6 is formed (FIG. 3B).

Next, a 3102 film 7 having a thickness of 1.47 tm is formed at about 800° C. by the thermal decomposition method of 5iH2C12 Ganu and N20 Ganu, and the groove 5 is filled with the SiO2 film 7 (FIG. 3C).

Next, a photoresist film is applied to the surface of the substrate, and the photoresist film is removed by dry etching, leaving the photoresist film 8 in the recessed portions, and the surface is made flat (FIG. 3D).

Then, the photoresist film 8.5102 film 7 is removed, and the surfaces of the isolation 5IO2 film 7 and the epitaxial layer 3 are made flat (FIG. 3E).

Next, a field S process 02 film 9. about 0.671 m thick was formed by selective oxidation. n+ type V vector region 10, p+ type pace region 11. Forming the n+ type emitter region 12 (
Figure 3F).

In this case, the base region 11 or emitter region 10 is 9
It is formed by diffusing impurities through heat treatment at 00°C or 950°C.

Problems to be Solved by the Invention In such a conventional method, since the CVD SiO2 film is buried in the 7^〒 formed on the Si substrate,
In the so-called LOCOS method, in which an insulation isolation region is formed by oxidizing a Si substrate, there is almost no stress due to the volume expansion caused by changing the silicon substrate into an 8102 film, and the stress during insulation isolation formation is smaller than in the LOCOS method. However, the coefficient of thermal expansion of 5102 (=o, 5x10
(,4)), StO thermal expansion coefficient (=2.5x1o
(/C:, )) is very large, and the diffusion of impurities after separation formation, especially the diffusion of the accumulation for forming the emitter region, is
Since the process is carried out at a higher temperature than the temperature 8Q○℃ during the formation of the S z O2 film, a large stress is added due to the thermal expansion of Si during arsenic diffusion in addition to the stress during the formation of the separated S102 film. Dislocations occur in the 81 substrate, causing abnormal diffusion of arsenic, forming so-called spikes or pipes, and causing an increase in collector-emitter leakage of the transistor.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having insulation isolation with little junction leakage using a simple method.

Means for Solving the Problems The present invention solves the problem of junction leakage by filling the trenches that will become insulation isolation regions with an insulating material at a temperature equal to or higher than the temperature during impurity diffusion after insulation isolation formation. It forms less insulation isolation.

Function The present invention has M! as described above. By filling the trench that serves as the three-edge isolation region with an insulator at a temperature higher than the temperature during impurity diffusion, it is possible to suppress the effects of stress due to thermal expansion of the SL during impurity diffusion, and prevent abnormal diffusion of impurities due to stress. It can prevent and reduce transistor junction leakage.

Embodiment FIGS. 1A-C and 2A-B are sectional views showing manufacturing steps of an embodiment of the semiconductor device of the present invention.

An n+ type buried region 2. is formed in a p type Si substrate 1 by a method similar to the conventional method. n-type epitaxial layer 3 with a thickness of 1/jm,
After forming the CV D S 102 film 4 and removing the CV D S 102 film 4 in the insulation isolation region, CVD-3
Using the iO2 film 4 as a mask, the St 2 film is etched to form a trench 5 with a depth of 2.5 to 3.571 m. Further, boron ions are implanted into the bottom of the groove 5 to form a channel puncher region 6 (FIG. 1A).

Next, by the thermal decomposition method of 5IH2Ce2 gas and N2o gas, a Si film with a thickness of 1.4 μm is produced at a temperature of about 960°C, for example.
An O film 7 is formed and the trench 6 is filled with an S 102 film 7. In this case, unlike the case where the groove 6 is filled with the S102 film 7 at 80Q°C as in the conventional case, the SiO2 film is
The membrane 7 will be filled.

After this, 5102d of the surface is
7, CV D S 102 film 4 is completely removed, the St○2 film 7 is left only in the groove 5, and the surface is made flat (first
Figure B).

Next, a field S102 film 9. of 0.671 m thick was formed using a method similar to the conventional method. After forming the n+ collector region 1°, the p+ type space region 11 and the n+ type emitter region 12 are formed at a temperature lower than the temperature at which the groove 5 is filled with the Sio2 film 7, for example, 960° C. or 900° C. (the first Figure C).

Filling the groove 5 with the S102 film γ at 800°C as in the conventional method.
at a higher temperature than that of the pace region 11° and the emitter region 12. In particular, when the emitter region 12 is diffused, the thermal expansion coefficient of SiO is about 6 times larger than that of S 102, so a large stress is generated at the interface 20 between Si and 3102 when S > 027 is filled due to the thermal expansion of StO. . If the viscosity of the SiO2 film 7 is very small or it shrinks due to heat, the interface 2Q between St and SiO2 when the SiO2 film 7 is filled will move according to the thermal expansion of SiO, as shown in Figure 2A. However, in reality, this is not the case, and a large stress is generated near the interface 20, and this stress causes abnormal diffusion of impurities such as arsenic that are not required to form the emitter region 12, resulting in spikes or pipes. 21 is formed, and collector-emitter leakage occurs. Stress can be alleviated by performing emitter diffusion at a temperature that reduces the viscosity of the SiO2 film 7, for example around 1060°C, but in this case, the base and emitter depths become deep and the breakdown voltage or speed of the transistor decreases. descend.

On the other hand, according to the present invention, by setting the temperature at the time of filling the SiO2 film 7 to a temperature higher than the temperature of the base and emitter diffusion in the subsequent process, the emitter region 1 is heated as shown in FIG. 2B.
During the 2 diffusion, no large stress is applied to the vicinity of the St and Sio2 interface 20 when filling the 5IO2 film 7 due to the thermal expansion of Si, so abnormal diffusion of arsenic does not occur, and no collector-emitter leakage occurs, resulting in good characteristics. A transistor can be formed.

Note that if excessive 0° is supplied when filling the Si○ film 7 and the temperature is as high as about 960°C, oxidation of St will occur simultaneously with the deposition of S 102, and the interface 20 between SL and SiO2 film 7 will be
Some thermal oxidation film is formed on the surface, and a stable interface can be formed.

Effects of the Invention As described above, in the present invention, stress due to thermal expansion of SiO during impurity diffusion is applied by filling the groove portion serving as the insulation isolation region with an insulator at a temperature higher than the temperature during impurity diffusion in the subsequent process. A method that can prevent abnormal diffusion of impurities due to stress and realize a semiconductor device having insulation isolation with little junction leakage,
It is extremely useful in practical terms.

[Brief explanation of the drawing]

FIGS. 1 and 2 are cross-sectional views of the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of the manufacturing process of a conventional semiconductor device. 5...Groove, 7...S*02 fl
i, 9...Field Si○2 film, 11...
...Base region, 12...Emitter region,
20...Si and 310 when filling Sio2 film 7
2 interface, 21...pipe. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure Otsu Figure 2 Figure 3 Figure 3

Claims (1)

[Claims] In the insulation isolation step of filling a groove formed in a semiconductor substrate with an insulator, the groove is filled with the insulator at a temperature equal to or higher than the temperature during thermal diffusion of impurities in a subsequent process. A method for manufacturing a semiconductor device.