JPS6016441A - Dielectric isolation of semiconductor substrate surface - Google Patents

Abstract

PURPOSE:To enable forming of an isolation region of minute width by determining the width of dielectric isolation of a semiconductor substrate in one photolithography process and permitting almost no variation of dimensions in later processes. CONSTITUTION:On a P type Si substrate 21, an N<+> buried region 22, an N type epitaxial layer 23 and an Si3N4 layer 24 are formed. On the film 24, a hole is opened and a groove 25, the depth of which reaches the substrate 21, is formed. Then, a polycrystalline Si film 28 is formed covering the film 24 and a film 27. Next, the film 28 is treated by anisotropic ion etching and left only at the side of the groove 25. Then, when polycrystalline Si is again formed, selective growth occurs using the film 28 at the side of the groove 25 as a nucleus and polycrystalline Si 29 is formed to fill the groove 25. In this method, forming of dielectric isolation region requires no thermal oxidatin process for a long time resulting no crystalline defects due to stress, etc. Since the width of an isolation region is determined by one photolithography process, the isolation region of a minute width can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for insulating and separating the surface of a semiconductor substrate, and more specifically, a method for separating semiconductor substrates by etching the surface of the substrate to form grooves and filling the grooves with an insulator or the like. Concerning a method for insulating isolation between elements, the structure of the conventional example and its problems In recent years, with the increasing integration of semiconductor integrated circuits, the so-called oxide film isolation method has been increasingly used as an isolation method between elements. became. However, as the oxide film separation method becomes more highly integrated, its shortcomings have appeared.

The conventional oxide film separation method will be schematically described below with reference to the drawings.

FIG. 1 is a cross-sectional view of a bipolar semiconductor integrated circuit device formed by applying oxide film separation technology, in which 1 is a P-type silicon substrate, 2a and 2b are Li" buried regions, and 3 is a P-type silicon substrate. Sonoku area, 4a.

4b is an N-type epitaxial growth layer, 6 is an oxide film insulation isolation region, 6a and eb are bird's heads, and 7a.

7b is Bird's Peak.

The bird's heads 6a and 6b are mainly caused by the turning-up of the nitride nitride film mask during selective oxidation, but the height of these parts usually reaches about % of the thickness of the oxide film insulation isolation region 6. Therefore, when a metal wiring layer is formed on the same, a disconnection may occur in the wiring layer. In addition, the bird's beak 7a is formed when oxygen diffuses and permeates in the lateral direction under the silicon nitride film mask in the selective oxidation process.
At the same time, the area of the N-type epitaxial growth layers 4a and 4b, which are device forming regions, is decreased and the cross-sectional shape is made complicated.

Furthermore, in order to thicken the oxide film insulating isolation region 6, it is necessary to lengthen the heat treatment time in the selective oxidation step, but this is because impurities in the N+ buried regions 2a and 2b are removed from the N-type epitaxial layer 4a. , '4b, causing a decrease in the collector-emitter breakdown voltage of the bipolar NPN transistor. In addition, an oxide film insulation isolation region 6
As the thickness increases, the height of the bird's head 6a, eb and the length of the bird's beak Ta, 7b increase proportionally, and the aforementioned disadvantages are also magnified. Due to this fact,
The thickness of the oxide film insulating isolation region 6 is usually 2 μm or less. However, the N-type epitaxial growth layer 4
The thickness of the N+ buried regions 2a, 2b (diffusion depth) is usually 1 to 2 pm.

1.5-2 μm, therefore i'J+ buried region 2a.

Therefore, the N+ buried deposit regions 2a and 2b cannot be brought very close to each other, and this point also becomes an obstacle to high integration.

Furthermore, in the selective oxidation process, since the silicon substrate is partially oxidized, stress due to the expansion of silicon during thermal oxidation is concentrated at the boundary area, and crystal defects that cause leakage current etc. are likely to occur. OBJECT OF THE INVENTION The present invention solves the problems of the conventional methods as described above, and provides a method for insulating and separating the surface of a semiconductor substrate in which the width of the separation region is small, the surface is flat, and the surface is suitable for high integration. It provides:

Structure of the Invention The present invention can be summarized as follows: a step of forming a nitride/recon film on the surface of a semiconductor substrate; and a step of selectively etching the semiconductor substrate using the silicon nitride film as a mask to form a groove. , forming a silicon oxide film on the surface of the groove, forming a polycrystalline silicon film on the entire surface of the silicon oxide film and the silicon nitride film, leaving the polycrystalline silicon film only on the side surfaces of the groove. This is a method for insulating and separating a semiconductor substrate surface, which includes the steps of anisotropic etching, and selectively growing polycrystalline silicon only on the polycrystalline silicon film to fill the trench. It is possible to form an isolation region with a wide width, and to suppress stress strain between the isolation region and an active region for forming a semiconductor element as much as possible, thereby realizing a semiconductor device with good electrical characteristics. DESCRIPTION OF AN EXAMPLE FIG. 2 is a flowchart showing the manufacturing process of a bipolar semiconductor integrated circuit device in the order of steps as an embodiment of the present invention. Hereinafter, the present invention will be described in detail with reference to this embodiment. First, as shown in FIG.
, a silicon nitride (Si3N4) film 24 is formed.

Next, as shown in FIG. 2(B), an etching opening is provided in a predetermined portion of the silicon nitride film 24, that is, a portion where an isolation region will be formed, by a normal photolithography method, and through this opening, for example, a reaction is performed. A groove 25 deep enough to reach the substrate 21 is formed by a method such as ion etching.

Then, using the silicon nitride film 24 as a mask, a channel region 26 is formed at the bottom of the trench 26 by ion implantation. Note that when reactive ion etching is used to form the grooves 26, the silicon nitride film 21
The groove has a substantially perpendicular shape to the opening, but as shown in the figure, there may be an undercut that cuts through the opening.

Then, as shown in FIG. 2(C), a silicon oxide (S10°) film 27 is formed on the surface of the groove 25. This silicon oxide film 27 is formed by a normal thermal oxidation method, and may have a thickness of 100 to 200 nm.

Next, as shown in FIG. 2(D), the well-known reduced pressure CVD1
KJl:l, a polycrystalline silicon film 28 is formed covering the entire surface of the silicon nitride film 24 and the silicon oxide film 27. According to the low pressure CVD method, the film is formed isotropically, and the film thicknesses on the silicon nitride film 24 and on the silicon oxide film 27 are approximately equal.

When this polycrystalline silicon film 28 is etched using a reactive ion etching method, as shown in FIG. The polycrystalline silicon film is removed from the planar portion of the silicon film 24.

When polycrystalline silicon is again formed on this by a CVD method containing a chlorine-based gas, for example, hydrogen chloride, as shown in Fig. 2 (
As shown in F), selective growth occurs using the polycrystalline silicon film 28 on the sidewall portion of the trench as a nucleus, and polycrystalline silicon 29 is generated to fill the trench.

Next, as shown in FIG. 2(G), the top of the polycrystalline silicon 29 is etched. The amount of etching at this time is such that the surface is 100 to 2
It is appropriate to make it as low as 0.00 nm. In addition,
The etching in this case may be either isotropic or anisotropic.

Thereafter, as shown in FIG. 2H, a silicon oxide film 30 is formed on the exposed surface of the polycrystalline silicon 29 by thermal oxidation. At this time, it is appropriate that the surface of the silicon oxide film 30 substantially coincide with the surface of the N-type epitaxial growth layer 23. Note that during thermal oxidation of the polycrystalline silicon 29, a portion of the N-type epitaxially grown layer is also oxidized through the silicon oxide film 27, but in general, the oxidation rate of polycrystalline silicon is higher than that of single crystal silicon. Since the width is also large, the expansion of the width of the separation region and the occurrence of bird's peaks due to this oxidation process are not large enough to cause problems.

Each element of the bipolar semiconductor integrated circuit is formed in the N-type epitaxial growth layer 23 by selective diffusion, but the steps for forming each element may be the same as in the conventional method.

In the step shown in FIG. 2A, a silicon oxide film (not shown) with a thickness of about 10 to 30 nm may be formed on the surface of the N-type epitaxial growth layer 23 before forming the silicon nitride film 24.

In FIG. 2(B), when forming the groove 25, the N+ buried region 23 is not penetrated, and the N-type epitaxial growth layer 2 is formed.
It may be formed to a depth that penetrates only 3. In this case, the N+ buried regions that need to be separated from each other must be formed separately in advance, but there is an advantage that the depth of the trench can be made shallow.

Furthermore, in the step shown in FIG. 2(H), by using a CVD method in which the polycrystalline silicon 29 is doped with impurities in advance, increasing the oxidation rate will cause the width of the isolation region to widen and the birds to form.・The generation of peaks can be further suppressed.0 The above embodiments have been explained in the process of forming the isolation region of a bipolar type semiconductor integrated circuit device, but they can also be applied to MO8 type semiconductor integrated circuit devices and their mixed type semiconductor integrated circuit devices. The same process can also be used as an isolation technology for circuit devices.

Effect of the invention According to the present invention, there are the following effects.

First, since a long thermal oxidation process is not required to form the insulation isolation region, crystal defects due to stress etc. do not occur.
A semiconductor integrated circuit device with good electrical characteristics can be obtained.

Second, the width of the isolation region is determined in a single photolithography process, and no dimensional changes occur in the subsequent steps, so a minute isolation region in one corner can be formed, resulting in higher density. can be achieved.

Thirdly, it is possible to increase the depth of the separation region; it is easy to do so, so by forming it deeper than the diffusion layers that you want to separate from each other, the thickness 1 on the plane between the diffusion layers can be made equal to the width of the separation region. high density can be achieved.

Since the surface of the fourth isolation region is flat and the difference in level from the active element forming region is small, there is no risk of disconnection of the metal wiring.

Sixth, by increasing the depth of the isolation region, it is possible to form the channel/stop region and other diffusions 11 without contacting each other, so the electrical 1fiJ pressure can also be increased, and the floating Capacity can also be reduced.

[Brief explanation of drawings]

Figure 1 is a sectional view of the main part of a conventional semiconductor device, Figure 2 (A)
~(H) is a process flowchart of the embodiment of the present invention 0 21... P-type silicon substrate, 22...,...
N+ buried region, 23... N-type epitaxial growth layer, 24... silicon nitride film, 26...
・Groove, 26...Door channel・Stotsuno 5 area,
27... Silicon oxide film, 28... Polycrystalline silicon film, 29... Polycrystalline silicon, 3
o... Silicon oxide film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 2 4 Figure 2

Claims (1)

[Claims] a step of forming a silicon nitride film on the surface of a semiconductor substrate; a step of selectively etching the semiconductor substrate using the silicon nitride film as a mask to form a groove; and forming a silicon oxide film on the surface of the groove. a step of forming a polycrystalline silicon film on the entire surface of the silicon oxide film and the silicon nitride film; a step of anisotropic etching leaving the polycrystalline silicon film only on the side surfaces of the groove; A method for insulating and isolating a semiconductor substrate surface, comprising a step of selectively growing polycrystalline silicon only on the film to fill the trench.