JPH01191476A - Semiconductor device - Google Patents

Abstract

PURPOSE:To perform stable circuit operation, by providing an insulating layer that is formed in a self-alignment manner with a gate electrode to the bottom surface parts of source and drain regions, decreasing parasitic capacitances, and fixing a potential through a semiconductor substrate since there is no insulating layer beneath the gate electrode. CONSTITUTION:A gate electrode 5 is formed. Thereafter oxygen ions are implanted, and heat treatment is performed. Oxide layers 7 are formed at regions other than a part directly beneath the gate electrode 5. Then, arsenic ions are implanted. N-type source and drain regions 8 are formed on the oxide layers 7. Since the oxide layers 7 are formed at the lower side of the regions 8, direct contact with the P-type silicon substrate 1 is prevented. Thus, junction capacitances can be decreased. A P-type region directly beneath the gate electrode 5 is constituted with a part of the P-type silicon substrate 1. A threshold voltage value is stabilized by electrical fixing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which an insulated gate field effect transistor (MOS) operates at high speed.

[Conventional technology]

Generally, in a semiconductor device using a MOS transistor as an element, it is preferable to reduce the parasitic capacitance of the source and drain diffusion layers of the MOS transistor in order to achieve high-speed operation of the element. For this reason, in a conventional semiconductor device of this type, as shown in FIG. 3, an oxide layer 7B is formed by, for example, oxygen ion implantation into a P-type silicon substrate 1, and a P-type silicon layer IA grown thereon is A MOS transistor is constructed by forming a source/drain region 8 made of an N-type diffusion layer, and further forming a gate electrode 5 via a gate oxide film 4 thereon.

According to this configuration, the junction capacitance between the source/drain region 8 and the P-type silicon substrate 1 can be reduced, and the speed of the device can be increased.

[Problem to be solved by the invention]

The conventional semiconductor device described above has a P-type silicon layer I forming the source/drain region 8 of the MOS transistor.
Since A is insulated from the P-type silicon substrate 1 by the oxide layer 7B, it is in a floating state and cannot be electrically fixed. Therefore, there is a problem in that the threshold voltage of the MOS transistor fluctuates and the circuit operation becomes unstable.

In addition, oxidized Ji7B is used as a gate oxide film and a P-type silicon substrate 1.
A parasitic MOS transistor is formed with the gate electrode and the N-type diffusion layer 8 as the source and drain, and there is also the problem that a leakage current is generated due to conduction of the parasitic MOS transistor.

An object of the present invention is to provide a semiconductor device that stabilizes circuit operation and prevents leakage current.

[Means to solve the problem]

The semiconductor device of the present invention includes a MOS transistor as an element, a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, and a gate electrode formed on the semiconductor substrate at both sides of the gate electrode. Conductivity type source
It consists of a drain region and an insulating layer formed on the bottom surface of the source/drain region in self-alignment with the gate electrode.

[Function] In the semiconductor device configured as described above, the one conductivity type semiconductor layer in the region immediately below the gate is continuously electrically connected to the semiconductor substrate, and can be electrically fixed through the semiconductor substrate. Ru.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(c) are cross-sectional views showing a first embodiment of the present invention according to its manufacturing process, and the structure of the embodiment will be explained below in the order of the steps.

First, as shown in FIG. 1(a), P-type silicon substrate 1 is coated with P.
+ type diffusion layer channel stopper 2. Field oxide film 3
to define an active region.

Approximately 300 gate oxide films 4 are grown in this area, N-type polysilicon is grown on top of the gate oxide film 4, and photoresist 6 is grown on the gate oxide film 4.
A gate electrode 5 of polysilicon is formed by anisotropic dry etching using as a mask.

After that, the acceleration energy was 80 KeV and the dose was IX 10.
Oxygen ions are implanted at 100° C. in a nitrogen atmosphere after removing the photoresist 6.
Heat treatment is performed using a halogen lamp for 0 minutes to form an oxide layer 7 in a region other than directly under the gate electrode 5.

Next, as shown in FIG. 1(b), the acceleration energy is 80Ke.
Arsenic is ion-implanted at a dose of 3.times.10"7 cm.sub.2 and heat treated at 900.degree. C. for 11 hours to form N-type source/drain regions 8 on the oxidized N7.

Furthermore, as shown in FIG. 1(c), an interlayer insulating film 9 is formed,
The process is completed by forming an aluminum electrode 10 doped with silicon through the contact hole.

According to this configuration, the oxide layer 7 is formed under the N-type source/drain region 8, and direct contact with the P-type silicon substrate 1 is prevented on this lower surface, so that the junction in this region is prevented. Capacitance can be reduced and high-speed operation of the element can be realized. Furthermore, since the P wall region immediately below the gate electrode 5 is formed of a part of the P-type silicon substrate 1, electrical fixation can be performed through the silicon substrate 1, and the threshold voltage can be stabilized. Can be done. Further, in this configuration, no parasitic MO3) transistor is formed, and no leakage current occurs.

In this embodiment, the oxide layer 7 is formed by implanting oxygen ions, but it may be formed as a nitride layer by implanting nitrogen ions. Further, although heat treatment is performed using a halogen lamp after oxygen ion implantation, heat treatment may be performed using an electric furnace.

FIGS. 2(a) to 2(C) are cross-sectional views showing a second embodiment of the present invention in the order of its steps.

First, as shown in FIG. 2(a), a P-type silicon substrate 1 is coated with P.
Channel stopper of mold diffusion layer 2. A field oxide film 3 is formed to define an active region. A gate oxide film 4 is formed in this active region, and N-type polysilicon is grown on it.
Using the photoresist 6 as a mask, the N-type polysilicon is etched to form the gate electrode 5.

Subsequently, using the photoresist 6 as a mask, the P-type silicon substrate 1 is etched by about 0.5 μm to form grooves 11 in locations corresponding to the source/drain regions.

Next, as shown in FIG. 2(b), an oxide film is grown on the entire surface by the CVD method, and the oxide film other than the bottom of the trench 11 is removed by an etch-back method using a photoresist.
An oxide layer 7A having a thickness of 0.3 μm is formed only on the bottom of the substrate. Subsequently, polysilicon is grown by the CVD method, and the polysilicon outside the upper edge of the oxide layer 7A is removed by an etch-back method using a photoresist, and a polysilicon layer 12 of 0.2 μm is formed only on the oxide layer 7A. do.

After that, as shown in Figure 2 (C), the acceleration energy is 80K.
Arsenic was ion-implanted into the polysilicon layer 12 at a dose of 3 x 10"7cm2 at 900"C.
A heat treatment is performed for 30 minutes to form a source/drain region 8A made of an N-type diffusion layer in which a part of arsenic is diffused directly below the gate electrode 5.

Thereafter, an interlayer insulating film 9 is formed, and an aluminum electrode 10 doped with silicon is formed to complete the process.

In this example, the oxide layer 7A can be formed at a low temperature, without changing the impurity distribution such as channel doping, and without deteriorating the gate oxide film, resulting in a high-performance and highly reliable MOS transistor. can be obtained.

[Effects of the Invention] As explained above, the present invention reduces parasitic capacitance in the source/drain regions by providing an insulating layer formed in self-alignment with the gate electrode at the bottom portion of the source/drain regions. Not only can the circuit operation be made faster, but since no insulating layer is formed in the semiconductor layer under the gate electrode, the potential can be fixed through the semiconductor substrate, which stabilizes the threshold voltage of the MOS transistor. This has the effect of ensuring stable circuit operation.

Further, since the insulating layer is formed by a self-alignment method using a gate electrode, there is no need for extra alignment or margin, and there is an effect that the degree of integration can be improved.

[Brief explanation of the drawing]

1(a) to 1(C) are sectional views showing the first embodiment of the present invention in the order of steps, and FIG. 2(a) to 2(C) are sectional views showing the second embodiment of the present invention. FIG. 3 is a sectional view showing the steps in the order of steps, and FIG. 3 is a sectional view of a conventional structure. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, IA... P-type silicon layer, 2... Channel stopper, 3... Field oxide film, 4... Gate oxide film, 5... Gate electrode, 6...
...Photoresist, 7.7A, 7B...Oxide layer, 8
, 8A... Source/drain region, 9... Interlayer insulating film, 10... Aluminum electrode, 11... Groove, 12
...Polysilicon. Figure 2

Claims (1)

[Claims] 1. A gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, source/drain regions of opposite conductivity type formed on the semiconductor substrate at positions on both sides of the gate electrode, and the source/drain regions of the opposite conductivity type. 1. A semiconductor device comprising an insulated gate field effect transistor including an insulating layer formed in a self-aligned manner with the gate electrode at a bottom surface of a drain region.