JPH01192128A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01192128A
JPH01192128A JP63017746A JP1774688A JPH01192128A JP H01192128 A JPH01192128 A JP H01192128A JP 63017746 A JP63017746 A JP 63017746A JP 1774688 A JP1774688 A JP 1774688A JP H01192128 A JPH01192128 A JP H01192128A
Authority
JP
Japan
Prior art keywords
bonding
wire
lead
chip
lead terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63017746A
Other languages
Japanese (ja)
Inventor
Susumu Sato
進 佐藤
Kazuo Terui
照井　一夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63017746A priority Critical patent/JPH01192128A/en
Publication of JPH01192128A publication Critical patent/JPH01192128A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
    • H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07552—Controlling the environment, e.g. atmosphere composition or temperature changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/521—Structures or relative sizes of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable performing a wire bonding process using a wire in length exceeding the length range of the wire causing resonance during a pressure fixing process by a method wherein a plurality of kinds of bonding positions of lead terminal are provided to be selected corresponding to the relative positions of a bonding part and the lead terminal. CONSTITUTION:The relative positions of a bonding pad on a chip and the lead terminal of a package 10 are confirmed by a camera 12 provided on the IC package 10 to feed the data to a position selecting means 13. The position selecting means 13 checks if the bonding position is contained within the range of resonance to select the optimum position from the multiple kinds of bonding positions previously stored in a memory 14 for feeding the positional data to a bonding controller 15. Finally, the bonding controller 15 drives a horn 16 corresponding to the positional data to perform the wire bonding process.

Description

【発明の詳細な説明】 〔概要〕 半導体装置の製造方法に係り、特に超音波圧着方式によ
るワイヤボンディング法に関し。[Detailed Description of the Invention] [Summary] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a wire bonding method using an ultrasonic pressure bonding method.

信頬性の高いワイヤボンディングを目的とし。Aimed at highly reliable wire bonding.

チップ（１）上のボンディングパッド（３）と。and bonding pads (3) on the chip (1).

該チップ（１）を搭載するパッケージ上に形成されたリ
ード端子（２）上のリードボンディング位置間にワイヤ
（４）をボンディングするに際し。When bonding wires (4) between lead bonding positions on lead terminals (2) formed on the package on which the chip (1) is mounted.

該リード端子（２）のボンディング位置を複数種類あら
かじめ準備しておき該ボンディングパッドとリード端子
との位置関係に応じて前記ボンディング位置を選択する
ことで、圧着時に共振を起こすワイヤの長さの範囲以外
の長さのワイヤでボンディングする様にしたことを特徴
とする半導体装置の製造方法をもって構成とする。By preparing a plurality of types of bonding positions for the lead terminal (2) in advance and selecting the bonding position according to the positional relationship between the bonding pad and the lead terminal, the length range of the wire that causes resonance during crimping can be reduced. The method of manufacturing a semiconductor device is characterized in that bonding is performed using a wire of a different length.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法に係り、特に超音波圧着
方式によるワイヤボンディング法に関する。The present invention relates to a method for manufacturing a semiconductor device, and particularly to a wire bonding method using an ultrasonic pressure bonding method.

半導体チップのワイヤボンディングには高信頼性が必要
とされる。High reliability is required for wire bonding of semiconductor chips.

〔従来の技術〕[Conventional technology]

第３図に半導体チップのワイヤボンディングの配置例を
示す。チップ１上のボンディングパッド３とパンケージ
上に形成されたリード端子２上のある位置（リードボン
ディング位置）とをワイヤ４でボンディングする。従来
、かかるワイヤボンディングを行う方法として超音波圧
着方式が用いも 与れている。FIG. 3 shows an example of the arrangement of wire bonding for semiconductor chips. A wire 4 is used to bond a bonding pad 3 on a chip 1 to a certain position (lead bonding position) on a lead terminal 2 formed on a pan cage. Conventionally, an ultrasonic pressure bonding method has been used as a method for performing such wire bonding.

第４図に超音波圧着方式ワイヤボンディングを示す。図
（ａ）はチップ側ボンディングの状態を示す。ホーンを
通して超音波でボンディングツールを振動させ、ワイヤ
４をチップ１上のボンディングパッド３に圧着し接合す
る。FIG. 4 shows ultrasonic pressure wire bonding. Figure (a) shows the state of bonding on the chip side. The bonding tool is vibrated with ultrasonic waves through a horn, and the wire 4 is crimped and bonded to the bonding pad 3 on the chip 1.

図（ｂ）はリード端子側ボンディングの状態を示す。チ
ップｌ上のボンディングパッド３に接合したワイヤ４を
ある長さｌでもってリード端子２上のリードボンディン
グ位置に接合する。この時。Figure (b) shows the state of bonding on the lead terminal side. A wire 4 bonded to a bonding pad 3 on a chip l is bonded to a lead bonding position on a lead terminal 2 with a certain length l. At this time.

長さｌのワイヤの固有振動数がホーンやツールを含む振
動系の振動とマツチングしてワイヤが共振し、ワイヤの
接合部を弱め、さらには接合部を破・断させてしまうこ
とがある。The natural frequency of the wire of length l matches the vibration of the vibration system including the horn and the tool, causing the wire to resonate, weakening the wire joint, and even causing the joint to break.

第５図に従来のボンディング法を示す。チップ１上のボ
ンディングパッド３とリード端子２上のリードボンディ
ング位置をワイヤ４でボンディングする。斜線で示した
範囲はそこにリードボンディング位置が来るとワイヤが
共振を起こす共振範囲である。従来、リード端子２上の
リードボンディング位置は予め決められていて１図（ａ
）に示すように搭載されるチップの位置が正常の場合は
リードボンディング位置は共振範囲に入らない。FIG. 5 shows a conventional bonding method. Bonding pads 3 on the chip 1 and lead bonding positions on the lead terminals 2 are bonded with wires 4. The shaded area is the resonance area where the wire resonates when the lead bonding position is located there. Conventionally, the lead bonding position on the lead terminal 2 has been determined in advance, as shown in Figure 1 (a).
) If the mounted chip position is normal, the lead bonding position will not fall within the resonance range.

しかし１図（ｂ）に示すように搭載するチップの位置が
ずれた場合、リードボンディング位置が共振範囲に入る
ことがあり、従来はこの状態でもボンディングが行われ
てしまっていた。However, if the position of the mounted chip shifts as shown in FIG. 1(b), the lead bonding position may fall within the resonance range, and conventionally bonding was performed even in this state.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明ではかかる問題点を解決するため、チップとリー
ド端子の位置関係でワイヤの長さを認識し、その長さが
共振する範囲内の時は、別の位置関係の長さを採用する
ようにした。In order to solve this problem, the present invention recognizes the length of the wire based on the positional relationship between the chip and the lead terminal, and when that length is within the resonance range, a length with a different positional relationship is adopted. I made it.

〔課題を解決するための手段〕[Means to solve the problem]

第１図は本発明のボンディング法である。 FIG. 1 shows the bonding method of the present invention.

超音波圧着方式によりチップ（１）上のボンディングパ
ッド（３）と、該チップ（１）を搭載するパッケージ上
に形成されたリード端子（２）上のリードボンディング
位置間にワイヤ（４）をボンディングするに際し、該リ
ード端子（２）のボンディング位置を複数種類あらかじ
め準備しておき該ボンディングパッドとリード端子との
位置関係に応じて前記ボンディング位置を選択すること
で、圧着時に共振を起こすワイヤの長さの範囲以外の長
さのワイヤでボンディングする様にしたことを特徴とす
る半導体装置の製造方法により上記課題は解決される。A wire (4) is bonded using an ultrasonic pressure bonding method between the bonding pad (3) on the chip (1) and the lead bonding position on the lead terminal (2) formed on the package on which the chip (1) is mounted. When crimping, by preparing multiple types of bonding positions for the lead terminal (2) in advance and selecting the bonding position according to the positional relationship between the bonding pad and the lead terminal, the length of the wire that causes resonance during crimping can be reduced. The above problem is solved by a method of manufacturing a semiconductor device, which is characterized in that bonding is performed using a wire having a length outside the range of the length of the semiconductor device.

（作用〕 本発明では第１図（ｂ）の如く搭載するチップの位置が
ずれ、チップが正常な位置の時のリードボンディング位
置ではワイヤが共振するおそれがある場合、そこを避け
て共振を起こさない位置Ｃリードボンディング位置を選
択する。リードボンディング位置は予めリード端子上に
複数箇所決めておき、チップのある位置ずれに対しては
あるリードボンディング位置、チップの別の位置ずれに
対しては別のリードボンディング位置と共振範囲を避け
る様にリードボンディング位置を選択できるようにして
おく。(Function) In the present invention, if the position of the mounted chip is shifted as shown in FIG. 1(b) and there is a risk that the wire will resonate at the lead bonding position when the chip is in the normal position, the resonance will be avoided by avoiding that position. Position C Select the lead bonding position.Predetermine multiple lead bonding positions on the lead terminal in advance, and set one lead bonding position for a certain positional deviation of the chip, and a different lead bonding position for another positional deviation of the chip. The lead bonding position can be selected so as to avoid the resonance range.

パッケージに搭載されたチップの位置ずれを自動的に計
測して、その情報から自動的に共振範囲を避けてリード
端子上のリードボンディング位置を選択してボンディン
グすることも可能である。It is also possible to automatically measure the positional deviation of the chip mounted on the package and use that information to automatically select and bond the lead bonding position on the lead terminal while avoiding the resonance range.

〔実施例〕〔Example〕

以下添付図により本発明の実施例について説明するが１
本発明はこれに限定されるものでない。Examples of the present invention will be explained below with reference to the attached drawings.
The present invention is not limited to this.

第２図は本発明の実施例であり、チップの位置ずれとリ
ードボンディング位置の位置関係を示している。FIG. 2 shows an embodiment of the present invention, and shows the positional relationship between the chip positional deviation and the lead bonding position.

図（ａ）は搭載されたチップが正常な位置にある場合で
、この時はリードボンディング位置も正常な位置■に決
める。Figure (a) shows a case where the mounted chip is in the normal position, and at this time, the lead bonding position is also set at the normal position (2).

図（ｂ）はチップが正常な位置よりもリード端子に近づ
いて搭載された場合で、この時リードボンディング位置
を正常な位置■にすると共振範囲に入るのであればそこ
を避けて例えばリードボンディング位置■を選択する。Figure (b) shows a case where the chip is mounted closer to the lead terminals than the normal position.At this time, if the lead bonding position is set to the normal position■, if it falls within the resonance range, avoid it and, for example, place the lead bonding ■Select.

図（Ｃ）はチップが正常な位置よりもリード端子から離
れて搭載された場合で、この時もリードボンディング位
置が正常な位置■だと共振範囲に入るのであればそこを
避けて例えばリードボンディング位置■を選択する。Figure (C) shows a case where the chip is mounted further away from the lead terminals than the normal position, and even in this case, if the lead bonding position is in the normal position ■ and it falls within the resonance range, avoid it and use lead bonding, for example. Select position ■.

上記実施例は第６図に示したボイディング装置により行
われる。図中、１０はＩＣパッケージでステージ１１の
上に置かれている。ＩＣパッケージの上に設けられたカ
メラ１２によりチップ上のボンディングパッドとパッケ
ージのリード端子との位置関係を認識し９位置選択手段
１３にその情報を伝える。位置選択手段ではボンディン
グ位置が共振範囲に該当するか否かを検知し、あらかじ
めメモリ１４に登録しである複数種類のボンディング位
置のうちから最適の位置を選択し、ボンディング制御部
１５に位置情報として伝える。ボンディング制御部１５
はそれに応じてホーン１６を駆動してワイヤボンディン
グを行う。The above embodiment is carried out by the voiding device shown in FIG. In the figure, 10 is an IC package placed on a stage 11. A camera 12 provided on the IC package recognizes the positional relationship between the bonding pads on the chip and the lead terminals of the package, and transmits this information to the nine position selection means 13. The position selection means detects whether the bonding position falls within the resonance range, selects the optimal position from among the plurality of bonding positions registered in advance in the memory 14, and sends the selected position to the bonding control unit 15 as position information. tell. Bonding control section 15
The horn 16 is driven accordingly to perform wire bonding.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に２本発明によれば、ワイヤボンディン
グ時のワイヤの共振を避けて、接合強度の劣化や断線の
ないワイヤボンディングを行うことができる。断線は検
査工程で不良として除くことができるが、接合強度の劣
化は封止工程後や使用者に渡った後に断線まで進むこと
もあるので。As explained above, according to the two aspects of the present invention, resonance of the wire during wire bonding can be avoided, and wire bonding can be performed without deterioration of bonding strength or disconnection. Although wire breaks can be eliminated as defects during the inspection process, deterioration in bonding strength may progress to wire breaks after the sealing process or after the product is delivered to the user.

問題である。本発明のワイヤボンディング法によれば、
それを避けることができる。That's a problem. According to the wire bonding method of the present invention,
You can avoid it.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明のボンディング法。 第２図は実施例。 第３図はワイヤボンディングの配置例。 第４図は超音波圧着方式ワイヤボンディング。 第５図は従来のボンディング法 第６図は本発明を実施するボンディング装置図である。 　図において。 １はチップ。 ２はリード端子。 ３はボンディングパッド。 ４はワイヤ を表す。 手・／プの位置か゛正常の塙含 （λ） 茎　ｌ　図 （＋２＞茶事パシン 麦＃！伊１ 草２図 フイヤボ゛ンデンン７の配置任・１ 茎　３　図 チップ便１ （の （＆） 革　５　図 FIG. 1 shows the bonding method of the present invention. Figure 2 shows an example. Figure 3 shows an example of wire bonding arrangement. Figure 4 shows ultrasonic crimp wire bonding. Figure 5 shows the conventional bonding method FIG. 6 is a diagram of a bonding apparatus implementing the present invention. In the figure. 1 is a tip. 2 is the lead terminal. 3 is the bonding pad. 4 is wire represents. The position of the hands/pens is normal. (λ) Stem diagram (+2> Tea ceremony Pashin wheat#! I1 Grass 2 Assignment of Fire Boyden 7 1 Stem 3 diagram Tip delivery 1 (of (&) Leather 5 diagram

Claims (1)

【特許請求の範囲】[Claims] 　超音波圧着方式によりチップ（１）上のボンディング
パッド（３）と、該チップ（１）を搭載するパッケージ
上に形成されたリード端子（２）上のリードボンディン
グ位置間にワイヤ（４）をボンディングするに際し、該
リード端子（２）のボンディング位置を複数種類あらか
じめ準備しておき該ボンディングパッドとリード端子と
の位置関係に応じて前記ボンディング位置を選択するこ
とで、圧着時に共振を起こすワイヤの長さの範囲以外の
長さのワイヤでボンディングする様にしたことを特徴と
する半導体装置の製造方法。A wire (4) is bonded using an ultrasonic pressure bonding method between the bonding pad (3) on the chip (1) and the lead bonding position on the lead terminal (2) formed on the package on which the chip (1) is mounted. When crimping, by preparing multiple types of bonding positions for the lead terminal (2) in advance and selecting the bonding position according to the positional relationship between the bonding pad and the lead terminal, the length of the wire that causes resonance during crimping can be reduced. 1. A method for manufacturing a semiconductor device, characterized in that bonding is performed using a wire having a length outside the range of length.
JP63017746A 1988-01-28 1988-01-28 Manufacture of semiconductor device Pending JPH01192128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63017746A JPH01192128A (en) 1988-01-28 1988-01-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63017746A JPH01192128A (en) 1988-01-28 1988-01-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01192128A true JPH01192128A (en) 1989-08-02

Family

ID=11952309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63017746A Pending JPH01192128A (en) 1988-01-28 1988-01-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01192128A (en)

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