JPH01192132A - Clock wiring process of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the slips in clock signals by wiring in a block or between blocks by a method wherein clock lines corresponding to the numbers of clock signals are laid down to encircle the periphery of respective blocks for individual arrangement wiring to feed clock signals from clock sources to the cells in blocks through the intermediary of these clock lines. CONSTITUTION:The title clock wiring can be made by laying down at least one clock line 51 in a channel around a block without fail as well as connecting a clock signal receiving line 53 from a clock source 3 and feeder lines to the blocks to nearby clock lines 51. Furthermore, in case of polyphase clock signals, it is feasible to connect the clock lines 51 laid down around blocks 21, 22, 23 as necessary to respective clock sources 3 for receiving clock signals to the blocks from respective clock lines 51.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a clock wiring method for a semiconductor integrated circuit device, and particularly to a clock wiring method for a device configured by a hierarchical layout method.

(Prior Art) When designing the layout of a semiconductor integrated circuit device that realizes a desired circuit operation by combinations of cells that realize basic functions and wiring between cells, as the scale of the circuit increases, the number of man-hours and Processing time increases exponentially, so it would take a huge amount of time and effort to lay out the entire circuit at once. Instead, divide the circuit into manageable blocks and create pre-designed macros. A hierarchical layout design method is widely used in which placement and routing is performed individually for each block except for blocks, and then wiring is performed between the blocks.

In the above layout, the number of cells (supplied cells) such as flip-flops to which clock signals should be supplied increases, and the clock signals supplied to each block must also be synchronized with each other. The connection method becomes an important issue. As a specific method,
As shown in Fig. 5(a), there are terminals (41, 42, 43) for connecting clock wiring on the sides of each block (21, 22, 23).
A possible method is to supply the clock signal into the block via this terminal and connect the clock generation source (3) to each block. However, with this method, the connection from the clock generation source to each block terminal is Since there are two paths, and there are differences in distance and resistance between them, there is a possibility that the characteristics of the clock signals supplied to each block will differ. When this problem comes to the level of supplied cells existing within a block, the deviation is further amplified depending on the number of cells (loads) and the distance from the terminal. For example, in FIG. 5(a), there are differences in the distances between the paths from the clock generation source to the clock terminals of each block, and in particular, the signal that has passed through block 22 is input to terminal 43. This will result in

Further, as shown in FIG. 5(b), if the positional relationship between the clock generation source and the clock terminal is not optimized, the influence becomes large, so optimizing the wiring method has become an important problem.

(Problems to be Solved by the Invention) As described above, in a circuit designed using a hierarchical layout method, the conventional clock wiring method does not allow the wiring path from the clock generation source to the clock terminal of each block and the wiring path within each block. There is a problem in that the characteristics of the clock signal vary due to differences in load conditions. SUMMARY OF THE INVENTION An object of the present invention is to provide a clock wiring method for a semiconductor integrated circuit device that solves these problems.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a semiconductor integrated circuit device designed using a hierarchical layout method, in which each block (block consisting of cells and macroblock), which is a unit of individual placement and wiring, is One or as many clock lines as necessary depending on the number of lock signals are laid around the block, and clock signals are supplied from the clock generation source to the cells within the block via these clock lines. This reduces deviations in clock signals between and within blocks due to wiring.

(Operation) According to the present invention, by diversifying the routes of clock signals supplied to each block in a semiconductor integrated circuit device designed using a hierarchical layout method and shortening the wiring distance, It becomes possible to reduce clock signal deviation without considering the load state of the clock signal. Furthermore, since the clock line is laid around the outside of each block, the necessary wiring only needs to be connected somewhere on this line, simplifying the wiring method.

(Example) The present invention will be described in detail below. Figure 1, Figure 2, Figure 3
4 are examples of layout results obtained by the clock wiring method to which the present invention is applied.

Assume that the chip is divided into, for example, three blocks (21, 22, 23).

In Fig. 1, a clock line (51) is laid so that there is always one in each channel around the block, and the clock line (51) is installed to take in the clock signal from the clock generation source (3) (53) and supply it to the inside of the block (52). is realized by connecting to adjacent clock lines. In addition, if the clock signal is multiphase, as shown in Figure 2, the required number of clock lines are laid around the block and each is connected to a different clock generation source, and the lines inside the block are It is possible to take in from each clock line.

In Figure 3, the same clock lines as in Figure 1 are laid out, but clock generation sources that are synchronized with each other are placed in two places, and a single phase clock signal is supplied by two sources. This is an embodiment for improving the characteristics of a clock signal.

FIG. 4 shows an example in which a clock line is laid at a position closest to the outer periphery of each block, and the blocks are connected by a number of straight lines (54) corresponding to the lengths of the opposing sides. In this example, by laying the clock line just outside the periphery of each block, there is no need to consider the position of the clock line connected to the inside of the block when wiring other blocks, making the wiring process easier. can do.

〔Effect of the invention〕

As described above, according to the present invention, clock lines are laid along the periphery of all blocks in a hierarchical layout, thereby simplifying the clock wiring method and transmitting clock signals between blocks and within each block. It is possible to reduce the deviation in the characteristics of

[Brief explanation of the drawing]

1 to 4 are plan views of the hierarchical layout results obtained by the clock wiring method of the present invention, and FIG. 5 is a plan view of the hierarchical layout results obtained by the conventional method. 1... Chip. 2, 21, 22, 23...block. 3...Clock generation source. 4, 41.42.43...Clock terminal. 5...Clock wiring. 51... Clock line surrounding the block. 52... Clock wiring for taking in signals into the block. 53... Clock wiring from the clock generation source. 54... Clock wiring for connection between blocks. Agent Patent Attorney Noriyuki Ken Yudo Matsuyama Kosoku No. 17 No. 2 Den 2+ / No. 50 No. 5 Seki

Claims (2)

[Claims] (1) When designing the layout of a semiconductor integrated circuit, the circuit components are divided into multiple blocks, and after performing placement and routing processing within each block except for pre-designed macroblocks, wiring between each block is performed. In a semiconductor integrated circuit device designed using the layout method, a clock line is laid out to surround all blocks using the wiring area (channel) between each block, and each block is connected from a clock generation source that supplies a clock signal to each A semiconductor integrated circuit device characterized in that clock wiring to cells to which a clock signal is to be supplied within a block is realized by connecting each cell or a generation source to any point on the clock line adjacent to the clock line. Clock wiring method. (2) By having multiple clock generation sources, connecting the clock wiring from each source to the clock lines laid around adjacent blocks, and operating each clock generation source in synchronization with each other. 2. The clock wiring method for a semiconductor integrated circuit device according to claim 1, wherein the same clock signal is supplied from a plurality of clock generation sources.