JPH01192189A - Manufacture of semiconductor light emitting element - Google Patents

Manufacture of semiconductor light emitting element

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Publication number
JPH01192189A
JPH01192189A JP1844988A JP1844988A JPH01192189A JP H01192189 A JPH01192189 A JP H01192189A JP 1844988 A JP1844988 A JP 1844988A JP 1844988 A JP1844988 A JP 1844988A JP H01192189 A JPH01192189 A JP H01192189A
Authority
JP
Japan
Prior art keywords
layer
groove
substrate
light emitting
active layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1844988A
Other languages
Japanese (ja)
Inventor
Kazuaki Mise
三瀬 一明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anritsu Corp
Original Assignee
Anritsu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anritsu Corp filed Critical Anritsu Corp
Priority to JP1844988A priority Critical patent/JPH01192189A/en
Publication of JPH01192189A publication Critical patent/JPH01192189A/en
Pending legal-status Critical Current

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  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To enable not only the formation of a groove without a strict control and a blocking layer on a substrate through a single process of growing a crystal but also these operations to be done at a high yield rate by a method wherein a groove wedge-shaped and provided with a vertical part in section is formed on a substrate extending in a stripe, and a crystal growth is performed onto the substrate in a single process. CONSTITUTION:A groove 21 is formed on a substrate 11 of a p-type InP single crystal through an etching. The groove 21 is shaped into a wedge form provided with a vertical part in section. A current blocking layer 31 of an n-type InP, a buffer layer 41 of a p-type InP, an active layer 61 of an InGaAsP, and a clad layer 71 of an n-type InP are continuously grown in succession through a liquid phase epitaxial growth performed once. In this process, if the buffer layer 41 is attached to be thicklish, the active layer 61 is shaped into a continuous layer, and if the buffer layer 41 is attached to be thinnish, the active layer 61 is separately provided above the groove 21, and when a laser is made to oscillate, the oscillation is simlified to be in a lateral mode.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はオプトエレクトロニクス分野、特に光通信光計
測器等の発光源として用いる半導体発光素子に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the field of optoelectronics, and particularly to a semiconductor light emitting device used as a light source for optical communication and measuring instruments.

(従来の技術) −aに、埋め込み形やV溝形の半導体発光素子を製造す
るには2回以上の結晶成長が必要であ;た、しかし、1
回の結晶成長で、ブロッキング層をも形成できる方が、
熱劣化も少なくなり、コストも低くなるので好ましい。
(Prior art) -a) In order to manufacture a buried type or V-groove type semiconductor light emitting device, two or more crystal growths are required;
It is better to be able to form a blocking layer with multiple crystal growths.
This is preferable because it reduces thermal deterioration and reduces costs.

その−例として、特開昭61−244085に開示され
ている半導体レーザがある。
An example thereof is a semiconductor laser disclosed in Japanese Patent Laid-Open No. 61-244085.

この従来の半導体レーザの構成及び製造工程を第2図を
参照して簡単に説明する。まず、第2図(A)において
、基板1としてP形1nP単結晶を用い、その<100
>基板面la上にエツチングマスクとしてSiO□を被
着し、フォトリソグラフィ技術を用いて基板結晶の<0
11>方向にストライプ状の窓を開け、続いて、ブロム
・メタノールを用いてこの窓を介して基板1に溝2をエ
ツチング形成し、第2図(A)に示すようなく011>
方向の溝が形成された基板1を得る。
The structure and manufacturing process of this conventional semiconductor laser will be briefly explained with reference to FIG. First, in FIG. 2(A), a P-type 1nP single crystal is used as the substrate 1, and its <100
>SiO□ is deposited on the substrate surface la as an etching mask, and the substrate crystal is
A striped window is opened in the 011> direction, and then a groove 2 is etched in the substrate 1 through this window using bromine methanol to form a groove 2 in the 011> direction as shown in FIG.
A substrate 1 in which directional grooves are formed is obtained.

次に、第2図(B)に示すように溝付き基板1を液相エ
ピタキシャル装置に入れ、n形1nP−!g電流狭窄層
3として成長させる。この時、n形■nP成長融液3a
はその表面張力の作用により溝2内に入り込まずにその
内面をぬらさない。
Next, as shown in FIG. 2(B), the grooved substrate 1 is placed in a liquid phase epitaxial apparatus, and the n-type 1nP-! G-current confinement layer 3 is grown. At this time, n-type nP growth melt 3a
does not enter the groove 2 due to its surface tension and does not wet its inner surface.

つぎに、表面張力の弱いP形InGaAsP成長融液で
バッファー層4を溝2内面迄成長させ、その上にp形1
nPの第1クラッド層5、InGaAsPの三日月状活
性層6、n形InPの第2クラッド層又、n第1 nG
aAs Pのキャップ層8を順次液相成長させ、第2図
(C)に示すようなウェハ構造を得る。その後で所要の
電極を蒸着して半導体レーザを得ることが知られている
Next, a buffer layer 4 is grown up to the inner surface of the groove 2 using a p-type InGaAsP growth melt having a low surface tension, and a p-type 1
A first cladding layer 5 of nP, a crescent-shaped active layer 6 of InGaAsP, a second cladding layer of n-type InP, and a first cladding layer 5 of n-type InP.
A cap layer 8 of aAsP is sequentially grown in a liquid phase to obtain a wafer structure as shown in FIG. 2(C). It is known to obtain a semiconductor laser by subsequently depositing the required electrodes.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、この従来の方法では、基板上に鳩尾状断
面の、ストライプ状に延在する溝の開口幅と深さを、厳
格に制御しなければ、n形InP層が溝の内面に迄形成
され、電流経路がなくなってしまうことがあるという問
題点があった。
However, in this conventional method, unless the opening width and depth of the grooves extending in a stripe pattern with a dovetail cross section on the substrate are strictly controlled, the n-type InP layer will be formed all the way to the inner surface of the grooves. However, there is a problem in that the current path may be lost.

この発明は、厳格な制御を必要としないで溝を形成でき
、さらに、基板上の結晶成長を1回の工程でブロッキン
グ層をも形成させ、しかも歩留り良く行うようにした半
導体発光素子の製造方法を提供することを目的とする。
The present invention is a method for manufacturing a semiconductor light emitting device, which allows grooves to be formed without requiring strict control, and also allows a blocking layer to be formed in a single process of crystal growth on a substrate, and which can be performed at a high yield. The purpose is to provide

〔課題を解決するための手段〕[Means to solve the problem]

この目的の達成するため、この発明は、基板に断面が垂
直部を有する楔形をしたストライプ状に延在する溝を形
成する工程と、基板上の結晶成長を−、回の工程で行な
えるようにしたことを特徴とする。
In order to achieve this object, the present invention has a process of forming a wedge-shaped groove extending in a stripe shape having a vertical section in a substrate, and a process of growing crystals on the substrate in two steps. It is characterized by the following.

〔作用〕[Effect]

このように溝の断面が、垂直部を有する楔形になったこ
とによって、電流ブロッキング層が、溝の垂直部で分断
され、そこに電流経路ができることになる。この時、溝
底部のブロッキング層は、半導体発光素子の電気的特性
(性能)には何ら悪影響を及ぼさない。
Since the groove has a wedge-shaped cross section with a vertical portion, the current blocking layer is divided at the vertical portion of the groove, and a current path is created there. At this time, the blocking layer at the bottom of the groove does not have any adverse effect on the electrical characteristics (performance) of the semiconductor light emitting device.

また、第1の導電形のバッファー層の膜厚を制御するこ
とにより、発光部となる活性層を隔設することができ、
さらに、レーザ発振した場合に、横モードの単一化も可
能となった。しかも、基板に溝を加工し易くなり、−旦
、溝付き基板を液相成長装置に入れた後は、温度プログ
ラムの制御のみでブロッキング層、バッフ1−層、活性
層、クラッド層等、発光に必要な各層を順次−回の液相
エピタキシャル成長で、活性層の形状を自由に制御する
ことができる。従って、成長層の界面が劣化したり汚染
されたりする恐れがないと共に、結晶成長の工程数を減
少でき、製造コストの低減及び歩留りの向上が達成でき
る。そして、電流狭窄に寄与するブロッキング層の存在
で、高注入高出力化が可能であり、さらに、活性層の熱
劣化を回避できることで、低閾値化が可能である。
In addition, by controlling the thickness of the buffer layer of the first conductivity type, the active layer that becomes the light emitting part can be separated.
Furthermore, it has become possible to unify the transverse mode when laser oscillates. In addition, it is easier to process grooves on the substrate, and once the grooved substrate is placed in the liquid phase growth apparatus, the blocking layer, buffer layer, active layer, cladding layer, etc. can be formed by simply controlling the temperature program. The shape of the active layer can be freely controlled by sequentially performing liquid phase epitaxial growth on each layer necessary for the process. Therefore, there is no risk of deterioration or contamination of the interface of the growth layer, and the number of crystal growth steps can be reduced, reducing manufacturing costs and improving yield. The presence of a blocking layer that contributes to current confinement makes it possible to achieve high injection and high output power, and furthermore, by avoiding thermal deterioration of the active layer, it is possible to lower the threshold value.

また、バッファー層を膜厚制御することにより活性層の
形状は三日月形に隔設される。これにより、横モードを
単一化できる。
Furthermore, by controlling the thickness of the buffer layer, the active layers are spaced apart in a crescent shape. This allows the transverse mode to be unified.

〔実施例〕〔Example〕

以下、図面を参照して本発明の実施例について説明する
Embodiments of the present invention will be described below with reference to the drawings.

第1図(A>、(B)、(C)は、本発明の実施例を示
す製造方法を説明するための説明図であり、第1図(A
)は基板の斜視図、第1図(B)。
FIG. 1 (A>, (B), and (C) are explanatory diagrams for explaining a manufacturing method showing an example of the present invention, and FIG.
) is a perspective view of the substrate, FIG. 1(B).

(C)は半導体発光素子の横断面図で示しである。(C) is a cross-sectional view of the semiconductor light emitting device.

基板11としてp形1nP単結晶を用い、その<100
>基板面11a上に5tsN4をプラグvCVD(Ch
emical  Vapour  Depositio
n)装置で堆積する。その上にレジストをスピンナーで
塗布しプリベイクする。
A p-type 1nP single crystal is used as the substrate 11, and its <100
>Plug 5tsN4 on the board surface 11a by vCVD (Ch
chemical vapor deposition
n) Depositing with equipment. A resist is applied on top of it using a spinner and prebaked.

次に、マスクアライナ−で基板結晶の〈011〉方向に
ストライプ状の窓が開くように、レジストを露光感光さ
せる。さらに、デベロッパーでパターン部のレジストを
除去した後、ポストベイクする。今度は、弗酸系エッチ
ャント(HF:NHmF=3:20)でパターン部のS
 t:+ N 、をエツチングしてから、アセトン又は
リムーバーでレジストを全部剥離する。こうした一連の
フォトリソグラフィ技術によって、ストライプ状の窓の
開いたエツチングマスクが被着した基板11にJ塩酸を
用いて、この窓を介して基板11に溝21をエツチング
形成する。この場合、溝21のストライプ方向を法線と
する面で切ったこの溝21の横断面形状は垂直部を有す
る楔形になる。垂直部は溝側面<011>面となる。(
第1図(A)参照)次に、弗酸系エッチャントでS i
、 N 、を全面剥離してから、この溝付き基板11を
液相エピタキシャル成長装置にセットする。n形InP
を電流ブロッキング層31として、p形1nPをパンフ
ァー層41として、InGaAsPを活性層61として
n形1nPをクラッド層71として、順次、1回の液相
エピタキシャル成長で、連続して各層を成長させる。こ
の時、バッファー層41を厚めに付着させると、第1図
(B)に示すように、活性層61が連続した層状の形状
になり、バッファー層41を薄めに付着させると、第1
図(C)に示すように、活性層61が溝21上に隔設さ
れ、レーザ発振した場合には、横モードが単一化される
Next, the resist is exposed to light using a mask aligner so that striped windows are opened in the <011> direction of the substrate crystal. Furthermore, after removing the resist in the pattern area with a developer, post-baking is performed. Next, remove S from the pattern area using a hydrofluoric acid etchant (HF:NHmF=3:20).
After etching t:+N, the resist is completely removed using acetone or a remover. Through this series of photolithography techniques, a groove 21 is etched into the substrate 11 on which an etching mask with striped windows is attached using J-hydrochloric acid through the windows. In this case, the cross-sectional shape of the groove 21 cut along a plane normal to the stripe direction of the groove 21 is wedge-shaped with a vertical portion. The vertical portion becomes the <011> surface of the groove side surface. (
(See Figure 1 (A)) Next, Si
, N is removed from the entire surface, and then this grooved substrate 11 is set in a liquid phase epitaxial growth apparatus. n-type InP
The current blocking layer 31, the p-type 1nP layer 41, the active layer 61 of InGaAsP, and the cladding layer 71 of the n-type 1nP layer are successively grown in one liquid phase epitaxial growth process. At this time, if the buffer layer 41 is deposited thickly, the active layer 61 will have a continuous layered shape, as shown in FIG.
As shown in Figure (C), when the active layer 61 is spaced above the groove 21 and laser oscillation is performed, the transverse mode is unified.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、基板に予め溝を
付け、1回の液相エピタキシャル成長により内部電流ブ
ロッキング層を有するダブルへテロ構造の半導体発光素
子を製造することができるので高注入高出力可能で低閾
値の半導体発光素子を得ることができる。しかも、発光
部の活性層を溝上に隔設すれば、単一基本横モードで発
振する特性を有する半導体発光素子を低コストで、歩留
り良く製造することができる。
As explained above, according to the present invention, it is possible to manufacture a double heterostructure semiconductor light emitting device having an internal current blocking layer by forming grooves in advance in a substrate and performing liquid phase epitaxial growth once, thereby achieving a high implantation level. It is possible to obtain a semiconductor light emitting device that can output and has a low threshold value. Moreover, by disposing the active layer of the light emitting part on the groove, a semiconductor light emitting device having a characteristic of oscillating in a single fundamental transverse mode can be manufactured at low cost and with high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(A)、(B)、(C)は本発明の実施例である
半導体発光素子の製造方法を説明するための説明図であ
り、第2図(A)、(B)、(C)は従来の半導体発光
素子の製造方法を説明するための説明図である。 1− p形1nP基板、1a・・−<lOO>基板面。 2・・・鳩鳥状の溝、  3・・・n形1nP電流狭窄
層。 4・・・p形1 nGaAs Pバッファー層。 5・・・p形1nPの第1クラッド層。 6 =・I n G a A s P活性層。 7・・・n形1nPの第2クラッド層。 8 ・−n形1 nGaAs Pキヤツプ層。 3a・・・n形1nP成長融液。 11・・・p形rnP基板。 lla・・・〈100〉基板面。 21・・・垂直部を有する楔形の溝。 31・・・n 形1 n P電流プロ°ツキング層。 41・・・p形1nPバッファー層。 61−1 n G a A s P活性層。 71・・・n形InPクラッド層。
FIGS. 1(A), (B), and (C) are explanatory diagrams for explaining a method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, and FIGS. 2(A), (B), and ( C) is an explanatory diagram for explaining a conventional method for manufacturing a semiconductor light emitting device. 1- p-type 1nP substrate, 1a...-<lOO> substrate surface. 2... Pigeon-shaped groove, 3... n-type 1nP current confinement layer. 4...p-type 1 nGaAs P buffer layer. 5... P-type 1nP first cladding layer. 6 = In Ga As P active layer. 7...N-type 1nP second cladding layer. 8 - n-type 1 nGaAs P cap layer. 3a...N-type 1nP growth melt. 11...p-type rnP substrate. lla...<100> Board surface. 21... Wedge-shaped groove having a vertical portion. 31...n type 1n P current blocking layer. 41...p-type 1nP buffer layer. 61-1 nGaAsP active layer. 71...n-type InP cladding layer.

Claims (2)

【特許請求の範囲】[Claims] (1)第1の導電形のIII−V族化合物半導体結晶基板
上に断面が垂直部を有する楔形のストライプ状に延在す
る溝をエッチングにより形成する工程と、該工程により
加工された該基板上に該溝の垂直部で分断された第2の
導電形のブロッキング層、第1の導電形のバッファー層
、発光部となる活性層および第2の導電形のクラッド層
を、1回の液相エピタキシャル成長により形成する工程
とを備えた半導体発光素子製造方法。
(1) A step of forming, by etching, a groove extending in a wedge-shaped stripe shape having a vertical section on a first conductivity type III-V compound semiconductor crystal substrate, and the substrate processed by the step. A blocking layer of the second conductivity type separated by the vertical part of the groove, a buffer layer of the first conductivity type, an active layer serving as a light emitting part, and a cladding layer of the second conductivity type are formed on the top by a single liquid solution. A method for manufacturing a semiconductor light emitting device, comprising a step of forming it by phase epitaxial growth.
(2)発光部の活性層を前記溝上に隔設したことを特徴
とする特許請求の範囲第1項記載の半導体発光素子製造
方法。
(2) The method for manufacturing a semiconductor light emitting device according to claim 1, wherein the active layer of the light emitting section is spaced apart above the groove.
JP1844988A 1988-01-27 1988-01-27 Manufacture of semiconductor light emitting element Pending JPH01192189A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1844988A JPH01192189A (en) 1988-01-27 1988-01-27 Manufacture of semiconductor light emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1844988A JPH01192189A (en) 1988-01-27 1988-01-27 Manufacture of semiconductor light emitting element

Publications (1)

Publication Number Publication Date
JPH01192189A true JPH01192189A (en) 1989-08-02

Family

ID=11971934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1844988A Pending JPH01192189A (en) 1988-01-27 1988-01-27 Manufacture of semiconductor light emitting element

Country Status (1)

Country Link
JP (1) JPH01192189A (en)

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