JPH01194046A - Memory access system - Google Patents

Abstract

PURPOSE:To speed up partial write access by reading out memory data only once from a memory for forming a check bit when data are written in the same word twice or more. CONSTITUTION:When a write access request is outputted from a CPU to a storage device 12, an access request address, control information and data are latched and processed and the succeeding access request is successively received from the CPU. When the 2nd access request is a 'WRITE' request, the addresses 42, 41 of the latched 1st and 2nd accesses are compared with each other by a comparator 9. When the addresses 42, 41 are included in the address range of the same processing unit as the compared result, writing data and a check bit are obtained by using memory data read out by the 1st read cycle, the CPU data of the 1st write cycle and the CPU data of the 2nd write cycle. Consequently, at least two access requests to the storage device can be executed only by one access and partial write access can be rapidly executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of Peng Dong] The present invention relates to a storage device for an information processing system, and particularly to a memory access method suitable for a device equipped with a circuit for error detection and correction.

[Conventional technology]

In information processing systems such as personal combinators, parity 't-ECC is used to increase the reliability of storage devices.
C error correcting code.

It is common to add a redundant code such as Error Corrgctig Code to data.

In the parity method, an extra parity bit is generally added to the data to indicate whether the number of 1 degrees included in byte (8-bit) data is odd or even. With this method, it is possible to detect when a 1-bit error occurs in data in units of bytes. However, correction of errors and
2-bit error detection is not possible.

On the other hand, in the ECC method, a plurality of redundant bits called check bits are added to data. The data width of the storage device must be 8 to correct a check bit error of 1 pit.
If it is pit width, it is 5 bits.

6 bits if the width is 16 bits, 7 bits if the width is 32 bits.
Although it requires a long pit, it is extremely reliable because it can correct 1-bit errors in data.

By the way, the CPU (central processing unit) of a personal computer, for example, Intel's 80585.

Motorola's 68020% 52-bit CPU also has data access instructions with a 16/8 pit width in order to maintain compatibility with software that handles conventional 16-bit to 78-bit data. Furthermore, since conventional software is often used in actual operations, 16/8-bit access is used more frequently than 32-bit access instructions.

On the other hand, the above-mentioned 52-bit CPU is generally designed to add an ECC redundant code in units of 52 bits. Therefore, when a part of this unit of 32 bits (4 bytes) is to be replaced (hereinafter referred to as partial write), it is performed as follows.

FIG. 2 shows data manipulation of partial write.

This is an example of partially writing 8-bit data '9AH' (H is an abbreviation for HEX and represents a hexadecimal number) into the memory. 32 bits of data are required to correctly generate check bits, but since the data 20 leaked from the CPU is 8 bits, the remaining 24 bits of data must be retrieved from memory. (Memory data 55
゜) If a 1-bit error has occurred in the memory data 35, use the check bit 36 to correct it.

Next, replace the second byte of the error-corrected data 59 with the CPU data value "9,4ff" and add the data 35.
get.

Further, the cutting tick bit 54 is generated from the cutting data 56.

This convolution data 33 and convolution check bit 34 are convolved in the memory.

When performing the above partial write, two accesses (hereinafter referred to as read mode 7 eye write cycle) are required, one for successive access and one for complimentary access, as detailed below.

Figure 5 is an example of a block prisoner of a storage device having an ECC function. The operation of the read modify write cycle during partial write will be explained below using this figure.

In this figure, the memory controller 10 is a circuit that receives an access request from a CPU (not shown), sends out a memory controller code 46, and controls the reading or writing of data from the memory 12. be. 4 is CPU
CPU data 2 of the 0th byte of data 20 from
This is a selector that selects the 1st and 0th bytes of memory data 29 in accordance with a byte enable signal 16 that specifies a retention byte from the CPU. Similarly, 5, 6, and 7 are the first bytes.

This is a selector that selects the second and third byte data. The syndrome generation circuit 14 is a circuit that generates information indicating the position of an error bit in data called a syndrome 39 from the memory data 55 and check bits 36 successively received from the memory 12. This circuit detects the position of an erroneous bit from 39 and inverts the erroneous data bit to correct the error.

When a partial write command is issued from the CPU, the memory controller 10 outputs a memory control signal 43 in order to read the memory data 35 and check pit 36 from the memory 12. The read memory data 55 and check bit 36 are latched into the register 13 by the memory control signal 43iC. The correction circuit 15 checks the check bits 38. The latch memory data 37 is corrected using the memory data 57 and the syndrome 39 generated by the syndrome generation circuit 14.

When the byte enable signal 16 indicates convolution of the second byte, the selector 6 of the second byte selects the CPU data 25 of the second byte, in the example of FIG.
Select l'. Remaining unwritten D-byte, 1st
Byte and 6th byte are memory data 29 and 5 respectively
Select 0.52. As a result, the consolidated data 33 is improved as shown in FIG.

The check pit generation circuit 11 uses the obtained data 5
A convolution check bit 34 is generated from 3.

When this is completed, the memory controller a-1o starts a write cycle, sends a memory control signal 43 indicating a write-in to the memory, and writes the convolution data ss and '4 check bit 64 to the memory 12. Finishes the read modify write cycle.

The operation of the read mode 7 eye-write cycle is shown in a timing chart as shown in FIG. 4 (α). This figure shows an example in which a dynamic RAM is used as the memory element, and the page mode WE is the details of the memory control signal 45 for high-speed access.

On the other hand, the same figure (bl is 52) contains data (hereinafter referred to as
It is called full light. ) is an example of a timing chart. In Figure 4, at full write, CPU data 21
~24 becomes the convolution data 53 as it is, and is stored in the memory 12.
Since the check bit 64 can be generated in one step without generating the memory data 35 from the memory, there is no need to perform the read mode 7 eye-write cycle (a convolution cycle with the same timing as a memory without an ECC function is sufficient).

As can be seen by comparing Figure 4 (α) and (b), partial write requires a read modify write cycle, so as mentioned earlier, compared to full write, it is about 2
Requires twice the access time.

Therefore, when executing a program that involves successive partial writes, for example, 80386 byte or word string instructions, the performance deteriorates compared to a memory device without ECC.

Although the reliability of the ECC type storage device is greatly improved as described above, there is a problem in that the memory write time is long.

As a conventional device to solve this problem, JP-A-61-11
There is one described in Publication No. 0247.

When reading data from the memory, it is checked whether an error has occurred in the data, and if it is a 1-bit error, the position of the error pit is determined and the error pit is corrected. However, if no error occurs or if there is a 2-bit error, it is not necessary to determine and correct the error pit position, so this processing time is not necessary.

Therefore, when a 1-bit error does not occur, the operation is performed in a cycle that shortens the time for determining and correcting the error pit position, and only when a 1-bit error occurs, the cycle time is extended and the error pit position is corrected. There are methods for determining and correcting the position. In the above conventional example, pay special attention to the partial write, and only if an error occurs in a byte other than the byte specified to be written to the CPU among the 32 pits of data.
This method attempts to improve the access time in the ECC method by treating bit errors and extending the cycle only in this case.

The configuration of the prior art is shown in FIG.

In this figure, parts with the same number as in Fig. 3 perform the same operations as those in Fig. 3. 44 is syndrome 59
This is a 1-bit error judgment circuit that detects whether a 1-bit error has occurred in a partial write, and only detects a 1-bit error when a 1-bit error occurs in byte data for which the byte enable signal 16 does not specify embedding. This is the circuit. 45 detects the error signal 46 outputted from the 1-bit error determination circuit 44 to the memory controller 10 in FIG. The case shown is a memory controller to which a circuit is added that performs a cycle in which the memory access time is longer than usual by the circuit delay of the correction circuit 15.

FIG. 6 shows an example of a timing chart of the prior art. 61 is a timing chart when a 1-bit error occurs during partial write, and 61 is a timing chart when no error occurs.

[Problem to be solved by the invention]

The above-mentioned conventional technology is effective in speeding up partial write cycles because the probability that a one-pit error will occur is generally very small (and most of the cycles are short cycles in which no errors occur).

However, as can be seen by comparing Figure 6 (bl) and Figure m4 (tbl), partial write access has a much longer access time than full write access due to low heat.
With string commands such as 4tic 80386, writes are continuous, so the deterioration in performance becomes noticeable.

An object of the present invention is to further speed up partial write access.

[Means to solve the problem]

In order to achieve the above object, the present invention takes into account that, due to the nature of programs, writes are often performed to consecutive addresses, and the same address is read as many times as the number of writes. If a word is written two or more times, reading of memory data from the memory for creating a check pit is performed only once.

[Effect]

That is, when there is a write access request from the CPU to the storage device, the access element address, control information, and data are latched and processed, and then the next access request is received from the CPU. When the second access request is a write, a comparator compares the latched addresses of the first and second accesses. If the result of the comparison is that the address is within the same processing unit, convolution data is created using the memory data successively received in one read cycle, the CPU data of the first write, and the CPU data of the second write. and get a check pit. This allows at least two access requests to the storage device to be
This can be done in one access.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In this figure, the same symbols as in FIGS. 3 and 5 perform the same operations as those in FIGS. 3 and 5. The data latch 3, the BE latch 1, and the address latch 8 are the CPU of the t'X access from the CPU to the storage device.
This is a latch circuit that latches the Uf-720, byte enable signal 16, and CPU address 41. The comparator 9 compares the latch address 42 latched in the address latch 8 with the CPU address 41 next requested for access by the CPU, and the result is an address of the same processing unit, which is within the range of 32 bits in this embodiment. This circuit sets the address-print signal 19 to 11 degrees. AND gate 35 connects address-km number 19 and byte enable signal 1
6, the address match signal 19 is 11
If it is 1, the byte enable signal 16 is enabled. 1st
The selector 4 of the latch byte enable signal 17 is set to
If byte-th data convolution is specified, select the 0-th byte latch data 25 as convolution data 33,
If the byte enable signal 18 specifies the fill-in of the 0th byte, the circuit selects the CPU data 21 of the 0th byte, and otherwise selects the correction memory data 29 of the 0th byte. be. Similarly, selectors 5 to 7 are selectors for the first byte, second byte, and third byte, respectively.

In this example, the first access request is the value of the second byte, °9.
Request to convolve i°. This is an example where the second access request writes the value "BCE" to the first byte of the address of the same processing unit. The seventh figure is a diagram showing the flow of data at this time.

First, a partial write command C is issued from the CPU to the storage device, and this is assumed to be a first access. ), partial write access information is stored in address latch 8. BE
The memory controller 10 latches the memory data 35 from the memory 12 to the latch 1 and the data latch 3 respectively.
Then, extraction of the check pit 36 is started.

While the memory controller 10 is performing a read operation, the comparator 9 receives the next access request (hereinafter referred to as a second access) from the CPU, and if the access request is a write, the CPU address 41 and latch address 42, which is latched into address latch 8.
Compare with. As a result, if both accesses are partial writes to addresses within the same address word, comparator 9 sets address match signal 19 to 1°.

When the read operation of the memory 12 is completed, the syndrome generation circuit 14 and the correction circuit 15 correct the error if a 1-bit error has occurred in the memory data 37. Make a selection. Since the first byte of the byte enable signal 16 is valid and the address match signal 19 is "1°," the CPU data 2 is the first byte.
Since the second byte of the latched byte enable 17 is valid, the value 'BCH@ of 2 is 1["9i" of the latch decoder 27, but which byte is the 0th byte and the 3rd byte? Since the conditions are not met, the 0th byte 29 and the 3rd byte 32 of the memory data 40 are respectively
are selected by selectors 4.5 and 6.7, respectively, and convolution data 33 is obtained.

Finally, the memory controller 10 stores this pledge data 3.
3 and the check bit 34 generated by the check bit generating circuit 11 are inserted, and the read modify write cycle is completed.

FIG. 8 is an example of the latter timing chart, where the CPU
Two convolution requests can be completed in - read-modify-write cycles.

Note that if the address match signal 19 is not 111, that is, if it is not a partial write to the address range of the same continuous processing unit, the second access is started. However, if the address match signal 19 is 11 degrees, it means that the first access and the second access are completed simultaneously by this access method.

Although the above embodiment uses the page mode of DRAM, it is also possible to use a static column method. Of course, normal write cycles and read cycles may be combined. Also, the data width of the memory is not 52 bits (it may be 16 bits, 64 bits, etc.).Also, in the example, addresses were compared for two writes, but addresses for five or more writes may be compared. .

〔Effect of the invention〕

According to the present invention, in a storage device having ECC@ capability,
When a partial write is sequentially requested from the CPU to the address range of the same processing unit to the storage device, two or more access requests can be processed in one read mode 7 eye write cycle.1. E-G Q
This has five effects: speeding up Zefunyaruite access while improving IT reliability.

[Brief explanation of the drawing]

FIG. 1 is a 10-step diagram of a storage device showing an embodiment of the present invention, FIG. 2 is a conceptual diagram for explaining partial write,
FIGS. 3 and 5 are block diagrams showing the configuration of a conventional storage device, FIGS. 4 and 6 are write cycle timing charts, and FIG. 7 is a diagram showing the data flow in the embodiment of the present invention. The conceptual diagram shown in FIG. 8 is a diagram showing a timing chart of an embodiment of the present invention. 1... BE latch 3... Data latch 4~
7...Selector 8 for 0th byte to 3rd byte...
・Address latch 9... Comparator 10...
Memory controller 11...Check pit generation circuit 12...Memory 14...Syndrome generation circuit 15...Correction circuit 2...AND gate Figure 4 (α) Wε: Read/ride control Figure 6 (α) Cb) Nishiorange B Meika 1) Eight Misu Yukare No. 8

Claims (1)

[Claims] 1. In a storage device having a data error correction function, control information of a write request from a CPU, a write address,
A latch means for latching the write data, and a means for comparing the write address latched by the latch means with the second write address requested by the CPU, and the result of the comparison by the comparison means is The write address latched by the latch means and the next write address requested from the CPU are within the processing unit range of the storage device, and the write request latched by the latch means and the next write address requested from the CPU A memory access method characterized by completing two write requests with one partial write operation when both write elements are partial writes. 2. In addition to executing write/read operations in response to write/read requests from the arithmetic processing unit (hereinafter referred to as CPU), it also has a 1-bit error correction function, and when a 1-bit error occurs in read data. In a storage device that can execute an operation by extending the cycle time, control information of a partial write request from the CPU, a write address,
A latch means for latching write data, a write address latched by the latch means at the time of the first partial write request, and the CP at the time of the second partial write request.
means for comparing the write address requested by U;
and means for completing the first and second partial write requests with one partial write operation when both write addresses compared by the comparing means are within a processing unit range of the storage device. memory access method.