JPH01194359A - Heterojunction bipolar transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a heterojunction bipolar transistor.

[Conventional technology]

In conventional heterojunction bipolar transistors, the entire base portion is uniform, as shown in Table 1 on page 3 of IEICE technical research report 5SD86-131° and in Figure 3 showing the manufacturing process. It is formed of an impurity-doped layer. This is because heterojunction bipolar transistors were designed primarily to reduce base resistance.

[Problem that the invention seeks to solve]

In this way, in a conventional heterojunction bipolar transistor, the base part is entirely composed of a uniform impurity doped layer, so
Carriers injected from the emitter spread throughout the base region. Therefore, compared to the number of carriers heading toward the collector, the number of carriers that diffuse to just below the base electrode and are absorbed by the base electrode becomes a non-negligible amount, resulting in the disadvantage that a large current amplification factor cannot be achieved. There is. This drawback becomes more noticeable as the base electrode is brought closer to the emitter-base junction through the adoption of the self-line process, etc., and thus becomes one of the factors inhibiting the miniaturization and integration of elements.

SUMMARY OF THE INVENTION In view of the above-mentioned circumstances, an object of the present invention is to provide a heterojunction bipolar transistor having a structure that can significantly reduce the amount of minority carriers injected from the emitter diffused directly under the base electrode.

[Failure to solve the problem]

According to the present invention, a heterojunction bipolar transistor includes a semi-insulating substrate, a collector layer formed on the semi-insulating substrate, a collector electrode drawn out from above the collector layer, and a collector layer formed on the collector layer. a base layer formed with a doped region, a base electrode formed on the heavily doped region of the base layer, a wide working bandgap emitter layer and an emitter formed on the lightly doped region of the base layer; and an electrode.

That is, the heterojunction bipolar transistor of the present invention has a feature that the base concentration in the region other than the region immediately below the emitter is doped with impurities at a higher concentration than in the region immediately below the emitter.

〔Example〕 The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view of a hetero-type bipolar transistor showing one embodiment of the present invention. According to this embodiment, the hetero-type bipolar transistor of the present invention includes: (a) an insulating substrate 1;
1, a second collector layer 10 and a first collector layer 9 which are sequentially laminated on this substrate 11, and a second collector layer 1.
0, a base layer formed on the first collector electrode 9 with different concentration regions 1 and 2, and a base electrode 3 formed on the high concentration region 2 of this base layer. and a wide band gap O emitter layer 4 formed in sequence on the low concentration region 1 of the base layer.
, emitter heterotransition layer 5, emitter cap layer 6
and the emitter electrode 7 o Here, the low concentration base region l directly below the emitter layer 4 is made of, for example, 5X beryllium.
It is made of gallium arsenide doped with 10"cm-3, and the high concentration base region 2 other than directly under the emitter is made of 1, for example,
It is made of gallium arsenide doped with 5 x 10" cm of beryllium. The other base electrode 3 is made of, for example, a gold-zinc-nickel alloy, and has a larger concentration than the low concentration region 1 and the high concentration region 2 of the base layer. For example, the emitter φ heterotransition layer 5 has a bandwidth of aluminum 0.3.gallium 0.7 arsenic, and the aluminum composition is linear from 0.3 to 0 from the emitter layer 4 to the emitter cap layer 6. Silicon-doped Ti3×10
cm-' of aluminum arsenic material, and the emitter cap layer 6 is formed, for example, of gallium arsenic material doped with silicon to I x 10 "cm=. Further, the emitter electrode 7 and the collector electrode 8 are both made of, for example, a gold-germanium-nickel alloy, and the first collector layer 9 is made of, for example, silicon in a 5×10
The second collector layer 10 is doped with 16 cm-" of gallium arsenide, and the second collector layer 10 is made of silicon, for example, I x 1018 cm-"
With doped gallium arsenide, the semi-insulating substrates 11 are each formed, for example, by a semi-insulating gallium arsenide substrate.

In the structure of this example, each semiconductor layer above the second collector layer 10 is created using, for example, molecular beam epitaxial growth or metalorganic chemical vapor deposition.
The base layers 1 and 2, the emitter layer 4, the emitter φ heterotransition layer 5, the emitter cap layer 6, the first collector layer 9, and the second collector layer 10 each have a thickness of 0.15 μm,
0.2μm, 0.01μm, 0.2μm, 0.5μm
m and 1 μm.

FIG. 2 is a sectional view of a heterojunction bipolar transistor showing another embodiment of the present invention. According to this embodiment, the low concentration base region 1 directly under the emitter layer 4 is formed by ion-implanting beryllium into a gallium arsenide material at an energy of 50 keV and a dose of 't5x10 cm. The high concentration base region 2 has a higher beryllium concentration than the low concentration base region 1 and has a lower implant energy, for example, an implant energy of 3
It consists of a gallium arsenide material ion-implanted with a 0 keV dose of 2 x 10"cm-". At this time, all seven layers other than this are the same as in the previous embodiment. In this example, since the base layer is entirely formed by ion implantation, an internal electric field is generated inside the base that causes the electric current to drift toward the crystallizer side. In addition, the high concentration region other than directly under the emitter is shallow, and the impurity concentration is low in the lower part of the region. Since the capacitance between the base and the collector becomes smaller, there is an advantage that both the current amplification factor and the cutoff frequency can be improved.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the impurity concentration is set to be different between the base region immediately below the emitter layer and the other base regions, so that the following equation is established between the two: Boltzmann Constant T: Temperature q: Elementary charge NBI: Base impurity immersion degree NBI just below the emitter
: There is a difference in the built-in potential described by the base impurity concentration other than directly under the emitter. This works to push back minority carriers injected from the emitter to the base from diffusing from the base region directly under the emitter to other regions, reducing the rate at which the injected minority carriers are absorbed into the base electrode. It is possible to improve internal transportation efficiency. That is, it can be extremely effective in improving the current amplification factor of a heterojunction bipolar transistor.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a heterojunction bipolar transistor showing one embodiment of the invention, and FIG. 82 is a sectional view of a heterojunction bipolar transistor showing another embodiment of the invention. 1...Low performance base area directly below the emitter, 2.
...Highly concentrated base region other than directly under the emitter, 3.
... Base electrode, 4 ... Wide band-gap emitter layer, 5 ... Emitter heterotransition layer, 6 ... Emitter cap layer, 7
...Emitter electrode, 8...Collector electrode, 9...First collector layer, 10...
Second collector layer, 11... Semi-insulating substrate. Agent: Susumu Uchihara, Patent Attorney Mr. Lee, right under 9, N-Su Rekkyo Z, Any,'
31 lower ↓ outside length Shimahiro skin
, Eni,, q, Hetero Dokaisha layer 6゜ 13, Ri, Yoyasobu 2 = 3) 1 Fig.

Claims (1)

[Claims] a semi-insulating substrate, a collector layer formed on the semi-insulating substrate, a collector electrode drawn out from above the collector layer, and a base layer formed with different concentration regions on the collector layer; A heterojunction type characterized by comprising a base electrode formed on a high concentration region of the base layer, and a wide band gap emitter layer and an emitter electrode formed on a low concentration region of the base layer. bipolar transistor.