JPH0350743A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the junction capacitance between a substrate and a source and drain by forming an insulating film layer below a source region and a drain region. CONSTITUTION:On a P-type silicon substrate 1, an insulating film 2 is arranged and patterned. By using molecular beam epitaxial growth method, a P<+> epitaxial growth layer 13 is formed, and sequentially a P<-> type epitaxial layer 4 is formed. After a gate insulating film 5 and a gate 6 are formed, a source 7 and a drain 8 are formed by using ion implantation method. Thereby the junction capacitance between the source 3, the drain 4, and the substrate 1 is remarkably reduced, so that the performance of a transistor is improved, and a MOSFET excellent in characteristics of resistance to short channel effect can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to an insulated gate field effect transistor (hereinafter referred to as
(abbreviated as MOSFET).

[Summary of the invention]

This invention reduces the junction capacitance between the substrate and the source/drain by providing an insulating WXN under the source and drain regions, and also increases the impurity concentration of the semiconductor layer directly under the channel region. This improves short channel resistance and enables high-speed operation and high integration.
Regarding OSFET.

[Conventional technology]

Miniaturization technology is essential for improving the performance and reliability of MOS FF and T. A problem currently faced in the miniaturization of MOSFETs is the short channel effect. This is because as the channel length decreases with miniaturization, the depletion layer extending toward the gate side contributes as a depletion layer on the drain side, as shown in Figure 2, resulting in a decrease in the threshold voltage of the transistor. It is something.

As a measure to prevent this short channel effect, the impurity concentration of the semiconductor layer directly under the +il gate insulating film is increased (11) The depth Xj of the source/drain diffusion layer is made shallow, and the effective lateral diffusion depth yj is Conventionally, L[)D (Lightly Do
ped drain) structures have been attempted.

[Problem to be solved by the invention]

However, the above conventional methods are not necessarily satisfactory and have the following problems. For example, L
The DD structure is formed using an ion implantation method, and the current control accuracy of the ion implantation method in the depth direction is 0.1 in the case of A3.
Due to the limited storage capacity, it was impossible to provide an LDD structure with a processing accuracy of 0.1- or less. In addition to the short channel effect, another problem associated with miniaturization is launch-up.
As a means to prevent this, a substrate with a high impurity concentration is used to lower the resistance of the substrate. However, in this case, the junction capacitance between the substrate and the source/drain increases, resulting in a problem that the dynamic characteristics of the transistor deteriorate.

[Means to solve the problem]

In order to solve the drawbacks of the above conventional methods, this invention
The following measures have been taken: First, in order to prevent the first short channel effect, as shown in FIG. 1, the impurity concentration on the surface side of the semiconductor layer directly under the gate is lowered, and the impurity concentration on the substrate side is increased. In order to realize this structure, in the present invention, 0
．． Molecular beam epitaxial growth method (M
BE) or molecular layer epitaxial growth (MLE)
is used.

In order to reduce the junction capacitance between the second substrate 1 and the source 7 and drain 8, the present invention uses a structure in which an insulating film layer is provided below the source region and the drain region, as shown in FIG. It is said that In order to realize this structure, the present invention employs a method of forming a semiconductor layer on an oxide film using lateral epitaxial growth, and then forming both the source 7 and drain 8 regions.

[Effect]

Since the impurity concentration in areas other than the vicinity of the surface of the semiconductor layer between both the source and drain regions is high, the decrease in carrier mobility is suppressed and the short channel effect is suppressed. Also sauce
The junction capacitance between both drain regions and the substrate can be significantly reduced, improving dynamic characteristics.

〔Example〕

Examples of the present invention are shown below in FIGS. 1 and 3 (al~(
This will be explained using C). In FIG. 3 fal, an insulating film 2 is provided on a P-type silicon substrate 1 and patterned. Next, in FIG. 3fbl, a molecular layer epitaxial growth method is used to form an epitaxial growth layer 1113 of Po, followed by an epitaxial growth layer 1'5n4 of P-. After this, see Figure 3 (gate insulation 1 at C1).
After forming II5 and gate 6, source 7 and drain 8 are formed using ion implantation. A cross-sectional view of the structure of the MOSFET manufactured through the above steps is shown in FIG. The characteristic points in Figure 1 are, first of all, P
The point is that an insulating film 2 is provided between the type silicon substrate 1 and the source 7, and between the P type silicon substrate 1 and the drain 8, respectively. As a result, the junction capacitance between the P-type silicon substrate 1 and the source 7 and the junction capacitance between the P-type silicon substrate 1 and the drain 8 are significantly reduced. The second feature in Figure 1 is
The semiconductor layer between the source 7 and the drain 8 consists of an epitaxial growth layer I3 with a high impurity concentration and an epitaxial growth layer 4 with a low impurity concentration. In one embodiment of the present invention, the thickness of the epitaxial growth layer I3 is, for example, about 2,500 layers, and the thickness of the epitaxial growth layer 4 is, for example, about 700 layers. Since the extension of the depletion layer to the side is suppressed, the structure has a structure in which short channel effects are less likely to occur.

〔Effect of the invention〕

As explained above, according to the present invention, the junction capacitance between the source 3, drain 4, and substrate 1 is significantly reduced.
The dynamic characteristics of the transistor are improved, and a MOSFET with excellent short channel resistance characteristics can be realized.

[Brief explanation of drawings]

FIG. 1 is a structural cross-sectional view showing one embodiment of the semiconductor device of the present invention, FIG. 2 is a structural cross-sectional view of a MOSFET having a conventional LDD structure, and FIG. It is a manufacturing process order cross-sectional view which shows an example of a manufacturing process.Semiconductor substrate insulation film epitaxial growth Ji [Epitaxial growth layer ■ Gate insulation film Gate source drain

Claims (2)

[Claims] (1) In a semiconductor device in which a gate is provided between both the source and drain regions via a gate insulating film, and the semiconductor layer directly under the gate has a conductivity type opposite to that of both the source and drain regions, A semiconductor device characterized in that an insulating film layer is provided below the region. (2) The semiconductor device according to claim 1, wherein the impurity concentration of the semiconductor layer directly under the gate increases as the distance from the gate insulating film increases.