JPH01196654A - Data buffer device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a method for outputting data that is input at high speed via multiple buses in any direction in the order in which it was input. The present invention relates to a data buffer device that performs unified FIFO processing.

(Prior art) In a data buffer device that performs high-speed FIFO processing on data input from both directions using two independent buses, it is considered to provide separate buffers for the input directions. It will be done.

However, in this case, for data that is input from both directions, in order to output data in any direction in the order in which it was input, in order to perform centralized queue management, multiple buffers that are differentiated according to the input direction are required. must be managed centrally and simultaneously, making the buffer management mechanism extremely complex.

(Problems to be Solved by the Invention) As described above, the unified FIFO processing for both directions in a data buffer device that can be considered numerically has a problem in terms of the complexity of the buffer management mechanism.

The present invention was made in view of these problems, and its purpose is to enable data to be input from both directions to two independent buses, and to provide FFI buffer management capabilities. An object of the present invention is to provide a data buffer device capable of outputting data at high speed in any direction in the order of input without unnecessary data.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the present invention provides a storage means for storing data on two independent buses in different areas on the same memory, and an access a switching means for switching the bus to be output; and information regarding the storage area type of the data stored in the storage means, the size of the bus to be output, and the data length, and the information is stored in the storage means based on this information. and control means for controlling data reading.

(Function) When data is written into the storage means, the bus to be written is first selected by the switching means, and the data on the selected bus is written into the first area of the storage means.

On the other hand, when data on a different bus is to be written, the switching means switches the writing bus, and the data on the switched bus is written into the second area of the storage means.

Furthermore, when data is written to the storage means in this manner, information regarding the output light bus and data length is stored in the storage area type of the stored data in the control means.

When reading data from the storage means, the control means reads the previously stored storage area type, output light bus, and data length from the internal storage section.

Then, one of the two areas of the storage means is selected from the storage area type information, the next buffer address to be output is obtained, the data of the data is read from that area, and the data is sent to the bus to be output.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing the configuration of a data buffer device according to an embodiment of the present invention.

As shown in the figure, this data buffer device
．． 3, a DMA control section 5.7, an external device 9.11, a buffer 13, a selector 15, and a buffer control section 17.

Buses 1.3 are independent buses. The DMA control unit 5.7 has external devices 9.11 to buffer 13, respectively.
When receiving a transfer request to , it performs DMA processing. buffer 1
3 contains the data on bus 1.3 and buffer 13
outputs the data stored on bus 1.3. FIG. 2 is an explanatory diagram of the memory on this buffer 13. As shown in the figure, the memory on this buffer 13 is
It consists of a first area 19 for storing data input from the bus 3, a second area 21 for storing data input from the bus 3, an input pointer 27.29, and an output pointer 23.25. Further, numerals 23 and 25 indicate the first area 1, respectively.
9 represents an output pointer indicating the data to be read next from the second area 21, and 27.29 represents an input pointer indicating the data to be written next from the first area 19 and the second area 21. Note that in the state shown in the figure, the first area 19
A4 byte data, a2 byte data, and a1 byte data are stored in , and the data to be read next by the output pointer 23 is the a4 byte data, and the input pointer 27 stores the data in the first area. The next data to be written to 19 will be written after the a1 byte data. Similarly, in the second area 21, the output pointer 25 and the input pointer 29 specify the next data to be read and the write location of the next data to be written.

The selector 15 selects the bus to be accessed from among the buses 1.3 based on a command from the buffer control unit 17. The buffer control unit 17 internally has an input pointer 33, an output pointer 31, and a FIFO table. This FIFO table stores information regarding the type of bus and data length to which the data stored in the buffer 13 should be output, and the third FIFO table controls reading of the data stored in the buffer 13 based on this information. The figure shows a FIFO table in the buffer control unit 17, and as shown in the figure, 8M of the bus to which data is to be output, that is, the transfer direction type and data length are stored in the FIFO table.

Further, reference numerals 31 and 33 indicate the output pointer and input pointer of the FIFO table. In the state shown in the figure, since the output pointer 31 points to a portion of data length a5, the data to be read from the buffer 13 is It can be seen that the data is output to the bus 3 and has a data length a5. Furthermore, when new data is written to the buffer 13 by the input pointer 33, the transfer direction type and data length are written to the next address.

Next, the operation of the data buffer device configured as described above will be explained.

When the buffer control unit 17 does not receive a write request to the buffer 13 from the external device 9.11, the buffer control unit 17
Repeat the reading process from .

The DMA control unit 5 transmits the transfer request to the buffer control unit 17, and the buffer control unit 17 interrupts the read process from the buffer 13, operates the selector 15 to make the bus 1 accessible, and starts the write process to the buffer 13. Start. Then, data from the external device 7L9 is written into the first area 19 of the buffer 13 by the DMA control unit 5. In this case, the data to be written starts at the address indicated by the input pointer 27. When the writing is completed, a transfer end signal is sent to the external device 9.
The data is transmitted to the buffer control unit 17 from there. However, if the external device 9 is a memory or the like and the number of data to be transferred is predetermined, the DMA control section 5 notifies the buffer control section 17 of the completion of the transfer. The buffer control unit 17 writes the data length ao of the data previously written to the buffer 13 and the type of bus to be read into the internal FIFO table. For example, when transferring data from the external device 9 to the external device 11, Write the bus type “3” and write “1” when returning from the external device 11 to the external device 9. The position of the FIFO table to be written is the input pointer 33.
is shown by. Furthermore, in the buffer 13, since ao bytes of data are written to the first area 19, the input pointer 27 is incremented by a predetermined amount.

However, if the input pointers 33 and 27 exceed the predetermined maximum value, they return to their respective starting addresses.

Thereafter, the buffer control section 17 returns to the read processing operation and performs the same operation as described above if there is a transfer request from the external device 9 (i.e., i.e., 11).

Next, the operation when data is not read from the buffer 13 will be explained.

The buffer control unit 17 reads the type and data length of the next bus to be output from the output pointer 31 in the FIFO table. For example, in FIG. 3, data with a data length a5 is indicated by the output pointer 31, and the output bus type of this data is "3", so the buffer control unit 17 controls the selector 15 to 3
The zero-order buffer control unit 17 that makes the
The data length a5 in the FO table is notified to the LIMA control section 7, a startup request is made to the DMAfliI control section 7, and the output pointer 31 is incremented to point to the position of the data length a4.

The DMA control unit 7 acquires control of the bus 3 and uses the buffer 13.
The data is read from the second area 21 of.

In this case, in the second area 21, the output pointer 25 indicates the beginning position of a5 bytes of data, so data is read from this position. Also, DMA
Since the data length a5 of the FIFO table is transmitted to the control unit 7, the output pointer 2 is
A55-byte data is read from the position not indicated by 5 and sent to bus 3. After the data transfer is completed, the DMA control unit 7 notifies the buffer control unit 17 of the completion of data reading. When the data reading is completed, the output pointer 25 of the second area 21 is incremented by the buffer control unit to the beginning position of the a3 byte data.

Also in the FIFO data, the output pointer 31 is incremented to a position indicating data of data length a4. In this case, if the output pointers 25 and 31 exceed the predetermined maximum value, the buffer control unit controls the output pointers 25 and 31 to return to their respective starting addresses.

In this way, this embodiment does not require complicated memory address management, and can immediately input data input from both directions via separate buses 1. Reading of data stored in the buffer 13 can be controlled by centralized queue management using a table. Furthermore, since bus 1 and bus 3 are completely separated, the influence of one bus does not propagate to the other.

[Effects of the Invention] As described above in detail, according to the present invention, data is input and output from both directions to two independent buses,
Moreover, a complicated buffer management mechanism is not required, and data can be outputted in a predetermined order at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data buffer device according to an embodiment of the present invention, FIG. 2 is a diagram showing the memory of the buffer 13, and FIG. 3 is a diagram showing the FIFO table in the buffer control unit 17. be. 1.3...Bus 5.7...DMA control unit 13...Buffer 15...
・・・・・・Selector 17・・・・・・・・・・・・
Buffer control unit Applicant Nippon Telegraph and Telephone Corporation Toshiba Corporation Agent Patent attorney Suyama Sa −

Claims (1)

[Claims] (1) Two independent buses are used in a buffer device that requires centralized queue management to output data input from both directions in any direction in the order in which it was input. a storage means for storing data on the buses in different areas on the same memory; a switching means for switching the bus to be accessed; a storage area type of the data stored in the storage means and a type of bus to be outputted; A data buffer device comprising: control means for storing information regarding a data length and controlling reading of data stored in the storage means based on this information.