JPH0119773B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a novel configuration of a binary counter frequently used in digital circuits.

Conventional configurations and their problems As is well known, the basic logic configuration of counters (including frequency dividers) that have been widely used in the past is six NAND gates or six NOR gates.
A unit stage is composed of an edge-trigger type T flip-flop with interconnected gates.As this type of counter has become the central part of all digital systems, especially digital LSIs, in recent years counters have become more popular. Many attempts have been made to reduce the number of gates in T flip-flops constituting a unit stage.

In particular, since I ² L ICs allow analog and digital circuits to be mixed together, their application to fields such as cameras, watches, and micromotor control circuits is remarkable.
An example was also presented in which the unit stage was reduced to four elements (the number of elements differs depending on whether the frequency is divided by a factor of 1 or when a reset function is added).

These cases can be found in the IEEE JOURNAL OF
SOLID-STATE CIRCUITS, Vol.SC-11, No.
6 (1976) PP 847-851 PATUCCI and L.
K.RUSSEL;'An I ² L Watch Chip with
Direct LED Drive' and IEEE Magazine Vol.SC−14,
No. 3 (1979) PP 657-660 U.
ABLASSSMEIER;'Camparison of Various
It is introduced in Binary Dividers in I ² L'.

However, these four-element flip-flops cannot provide an inverted output as an output signal, or require a special structure different from conventional ones.

Furthermore, as shown in Table 1 of the latter paper, these four-element flip-flops had a problem in that the usable limit frequency was significantly lowered due to their special configuration.

Purpose of the Invention The present invention realizes a binary counter in which the chip size for constructing a unit stage can be made smaller than before, or in other words, a unit stage can be constructed with a smaller number of wires and elements.

Structure of the Invention The binary counter of the present invention includes a first gate pair consisting of first and second matching gates whose respective first input terminals and output terminals are cross-coupled connected, and each of the first input terminals and the second matching gate. and a third and fourth coincidence gate whose output terminals are cross-coupled connected, and whose second input terminals are supplied with the output of the first coincidence gate and the output of the second coincidence gate, respectively. a pair of gates, a trigger signal from the previous stage is supplied to a first input terminal, an output of the first coincidence gate is supplied to a second input terminal, and the output is transmitted to the first and second coincidence gates. a fifth coincidence gate for supplying a second input terminal; means for supplying the output of said second pair of gates to a third input terminal of said first and second coincidence gate; and said first coincidence gate; means for supplying the output of the gate as a trigger signal to the next stage; and means for supplying the output of the fifth coincidence gate constituting the next unit stage to the fourth input terminal of the second coincidence gate. The device is characterized in that a plurality of unit stages are connected in cascade to form a unit stage, thereby reducing the number of elements or wiring per unit stage.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a logical configuration diagram of a 4-bit binary counter in an embodiment of the present invention _.
is the input terminal to which the clock signal is applied, terminal Q ₀ ,
Q ₁ , Q ₂ , Q ₃ are the 1st bit, 2nd bit, and
These are count output terminals for the 3rd and 4th bits.

In FIG. 1, NAND gates 11, 12, 13,
14, 15, and 16 constitute a first bit unit stage 100, and the unit stage 100 is a unit stage for supplying a trigger signal to a second bit unit stage 200 to which the present invention is applied. , it has the same function as a normal T flip-flop with a differential pulse generation circuit added to the output side.

In the unit stage 200, each input terminal and output terminal are cross-coupled.
The NAND gate 21 and the NAND gate 22 constitute a first gate pair 211, and the similarly connected NAND gate 23 and NAND gate 24 constitute a second gate pair 212.

Further, the output terminals of the NAND gates 21 and 22 are connected to other input terminals of the NAND gates 23 and 24, respectively, and the NAND gates 21 and
22 second input terminals are both connected to the output terminal of the NAND gate 25, and third input terminals are connected to the output terminals of the NAND gates 24 and 23, respectively. Furthermore, the first input terminal 25a of the NAND gate 25 is connected to the unit stage 10.
0, the second input terminal 25b is connected to the output terminal of the NAND gate 21, and the fourth input terminal of the NAND gate 22 is connected to the Configuring the stage unit stage 300
The output of the NAND gate 35 is supplied, and the
The output terminal of the NAND gate 21 is connected to the first input terminal of the NAND gate 35.

The unit stage 300 has NAND gates 31, 3
2, 33, 34, 35, and an inverter 36 in the same manner as the unit stage 200, and in the unit stage 400, the NAND gate 2
Inverter 45 is used instead of 5,
The fourth input terminal of NAND gate 42 is omitted.

Now, since the circuit shown in FIG. 1 is particularly effective in reducing the number of elements when implemented in I ² L, we will summarize the operation based on the circuit connection diagram in which the unit stages 100 and 200 are configured with I ² L transistors. Explain.

First, FIG. 2 is a circuit connection diagram in which the logical configuration of the unit stage 100 in FIG. 1 is realized by an I ² L circuit.
In FIG. 2, the base of transistor 101 is connected to clock pulse input terminal ₀ , and the base of transistor 101 is connected to clock pulse input terminal 0.
The collector 1a is connected to the base of the transistor 102, and the second collector 1b is connected to the base of the transistor 102.
The third collector 1c is connected to the base of the transistor 106, the first collector 2a of the transistor 102 is connected to the drive output terminal ₀ , and the second collector 2b is connected to the base of the transistor 103. The third collector 2c is connected to the base of the transistor 107, the fourth collector 2d is connected to the base of the transistor 104, and the third collector 2c is connected to the base of the transistor 104.
The first collector 3a of 03 is the transistor 10
The second collector 3b is connected to the base of the transistor 107, and the third collector 3c is connected to the base of the transistor 105.

Further, the first collector 4a of the transistor 104 is connected to the base of the transistor 105, and the second collector 4b is connected to the first bit output terminal.
Q ₀ , the third collector 4c is connected to the base of the transistor 103, the first collector 5a of the transistor 105 is connected to the base of the transistor 104, and the second collector 5b is connected to the inversion of the first bit. connected to output terminal ₀ ,
The third collector 5c is connected to the base of the transistor 102.

Furthermore, the first collector 6a of the transistor 106 is connected to the base of the transistor 107, and the second collector 6a of the transistor 106 is connected to the base of the transistor 107.
The third collector 6c is connected to the base of the transistor 102, and the first collector 7a of the transistor 107 is connected to the base of the transistor 106.

Now, Fig. 3 shows the signal waveforms of each part of the circuit of Fig. 2, and the second, third, and
The signal waveforms of the fourth collector are the first, second, and
It is assumed that the signal waveform of the third collector has a delay equivalent to one half of the signal transmission delay between gates.

In Fig. 3, a is the clock pulse input to clock pulse input terminal ₀ , b~d, e~h, i~
k, l~n, o~q, r~t and u are the first to third collectors of the transistor 101, respectively;
First to fourth collectors of transistor 102, first to third collectors of transistor 103, first to third collectors of transistor 104, first to third collectors of transistor 105, transistor 10
6 and the first collector of the transistor 107. In an actual circuit, for example, the first collector of the transistor 101
The collector 1a is connected to the transistors 103 and 10.
5, 106 collectors 3a, 5c, and 6c, a waveform different from the signal waveform shown in FIG. 3 appears, but in order to make the explanation of the operation easier to understand, in FIG. It shows the collector waveforms of each collector when it is separated from other collectors.

Now, the transistors 101, 104 in FIG.
When the output level of 107 is “0” (here “L”)
(the level corresponds to logic 0, and the "H" level corresponds to logic 1), transistors 102,1
03, 105, and 106, at time _t1 , the level of the base of the transistor 101 changes from "1" to " ₀ " as shown in FIG. If the transition occurs, then the first collector 1a of the transistor 101
The level of the second collector 1b and the third collector 1c shift to "1" one after another.

When the level of the first collector 1a of the transistor 101 shifts to "1", the first collector 3a of the transistor 103, the third collector 5c of the transistor 105, and the transistor 106
Since the level of the third collector 6c of the transistor 102 is all "1", the level of the first collector 2a of the transistor 102 shifts to "0", and the level of the second collector 2b, the third collector 2c, and the transistor 102 shifts to "0". The fourth collector 2d shifts to "0" one after another.

When the level of the third collector 2c of the transistor 102 shifts to "0", the transistor 10
The output level of the first collector 7a of the transistor 101 shifts to "1", and at this point the output level of the first collector 7a of the transistor 101 shifts to "1".
Since the level of the collector 1c is "1", the level of the first collector 6a of the transistor 106 shifts to "0", and then the level of the second collector 6a of the transistor 106 shifts to "0".
b, the level of the third collector 6c becomes “0” one after another
to move to.

When the level of the third collector 6c of the transistor 106 shifts to "0", the level of the first collector 2a of the transistor 102 returns to "1", and the level of the second collector 2b, the third collector 2c,
The level of the fourth collector 2d also returns to "1" one after another.

On the other hand, at the time when the level of the fourth collector 2d of the transistor 102 shifts from "1" to "0" before returning to "1", the level of the first collector 4a of the transistor 104 shifts to "1", Subsequently, the levels of the second collector 4b and the third collector 4c also shift to "1".

When the level of the first collector 4a of the transistor 104 shifts to "1", since the level of the third collector 3c of the transistor 103 has already become "1", the level of the first collector 5a of the transistor 105 shifts to "0". ", and the levels of the second collector 5b and the third collector 5c successively shift to "0".

At time _t2 , when the level of the base of the transistor 101 shifts to "1", the level of the first collector 1a of the transistor 101 shifts to "0", followed by the level of the second collector 1b and the third collector. The level of 1c also shifts to "0" one after another.

When the level of the third collector 1c of the transistor 101 shifts to "0", the transistor 10
6 first collector 6a, second collector 6b, third collector
The level of collector 6c shifts to "1" one after another,
By shifting the level of the first collector 6a of the transistor 106 to "1", the transistor 10
The level of the first collector 7a of clock pulse 7 shifts to "0" in preparation for the arrival of the leading edge of the clock pulse at time _t3 .

At time _t3 , when the level of the base of the transistor 101 shifts to "0", the level of the first to third collectors shifts to "1".

When the level of the second collector 1b of the transistor 101 shifts to "1", the second collector 2b of the transistor 102, the third collector 4c of the transistor 104, and the transistor 106
Since the level of the second collector 6b of the transistor 103 is "1", the level of the first collector 3a of the transistor 103 shifts to "0", and then the level of the second collector 3b and third collector 3c of the transistor 103 shifts to "0". The level also shifts to "0".

As the output level of the second collector 3b of the transistor 103 shifts to "0", the level of the first collector 7a of the transistor 107 shifts to "1", and on the other hand, the output level of the third collector 3c of the transistor 103 shifts to "1". As the level shifts to "0", the level of the first collector 5a of the transistor 105 shifts to "1".

When the level of the first collector 7a of the transistor 107 shifts to "1", the transistor 10
The level of the first collector 6a of the transistor 106 shifts to "0", and the level of the second collector 6b and third collector 6c of the transistor 106 also shifts to "0", and the level of the second collector 6b of the transistor 106 shifts to "0". Due to the transition to "0", the level of the first collector 3a of the transistor 103 returns to "1".

Note that during this time, the first
As the level of the collector 5a shifts to "1", the output level of the transistor 104 shifts to "0".

At time _t4 , when the level of the base of the transistor 101 shifts to "1", the output level of the transistor 101 shifts to "0", as at time _t2 , and as a result, the level of the base of the transistor 101 shifts to "0".
The output level of transistor 107 shifts to "1", and further the output level of transistor 107 shifts to "0".

Thereafter, in the same way, each time the level of the base of the transistor 101 changes, in other words, each time the level of the clock pulse input terminal ₀ changes, the output level of each transistor changes repeatedly.
The level of input terminal ₀ of the circuit in Figure 2 is as shown in Figure 3 a.
When the drive output terminal changes as shown in
Signal waveforms as shown in FIG. 3 e, m, and p appear at the output _terminal Q ₀ of the 0, 1st bit, and the inverted output terminal ₀ of the 1st bit, respectively.

In other words, the circuit shown in FIG. 2 can be considered to be a circuit in which the function of a differential pulse generation circuit is added to an ordinary T flip-flop.

Now, FIG. 4 is a circuit connection diagram in which the logical configuration of unit stages 200 and 300 in FIG. 1 is realized by an I ² L circuit. In FIG. 4, a transistor 20 whose base is connected to the trigger signal input terminal ₁
1, the first collector 201a is the transistor 202
The second collector 201b of the transistor 203 is connected to the base of the transistor 203, the first collector 202a of the transistor 202 is connected to the base of the transistor 201, and the second collector 201b of the transistor 202 is connected to the base of the transistor 201.
The collector 202b is connected to the drive output terminal ₁ , the third collector 202c is connected to the base of the transistor 204, and the fourth collector 202c is connected to the base of the transistor 204.
2d is connected to the base of the transistor 203, and the first collector 20 of the transistor 203
3a is connected to the base of the transistor 205,
The second collector 203b is connected to the transistor 20
Connected to the base of 2.

Furthermore, the first collector 204a of the transistor 204 is connected to the second bit output terminal _Q1 , the second collector 204b is connected to the base of the transistor 205, and the third collector 204b is connected to the base of the transistor 205.
4c is connected to the base of the transistor 203 and the first collector 20 of the transistor 205.
5a is connected to the base of the transistor 204, and the second collector 205b is connected to the base of the transistor 202.

Further, the base of a transistor 206 is connected to the feedback signal supply terminal F ₁ , and the first collector 206 a of the transistor 206 is connected to the base of the transistor 203 .

The unit stage 300 includes transistors 301 and 3
02, 303, 304, 305, 306, and the third collector 3 of the transistor 301
It has the same configuration as the unit stage 200 except that the terminal 01c is connected to the feedback terminal _B2 .

Now, the transistors 201, 204 in FIG.
When the output level of transistors 301 and 304 is "0" and the output level of the other transistors is "1", the level of the base of the transistor 201 at time _t11 is as shown in FIG. 5aa. , the first collector 201a of the transistor 201,
Further, the level of the second collector 201b shifts to "1".

the first collector 201 of the transistor 201;
When the level of a shifts to "1", the level of the second collector 203b of the transistor 203 and the second collector 205b of the transistor 205 are both "1" in advance, so the level of the first collector 202a of the transistor 202 changes. “0”
Then, the levels of the second collector 202b, the third collector 202c, and the fourth collector 202d successively shift to "0".

the third collector 202 of the transistor 202;
When the level of c shifts to "0", the level of the first collector 204a of the transistor 204 shifts to "1", and then the level of the second collector 204a of the transistor 204 shifts to "1".
b, the level of the third collector 204c shifts to "1" one after another.

a second collector 204 of the transistor 204;
When the level of b shifts to "1", since the level of the first collector 203a of the transistor 203 has become "1" in advance, the level of the transistor 20
The level of the first collector 205a of No. 5 shifts to "0", and subsequently the level of the second collector 205b also shifts to "0".

the second collector 205 of the transistor 205;
When the level of the transistor 202 shifts to "0", the output level of the transistor 202 returns to "1", and the first
Collector 202a, second collector 202b, third collector 202c, fourth collector 202d
The level returns to "1" one after another.

the first collector 202 of the transistor 202;
Assuming that the level of the trigger signal input terminal ₁ has shifted to "1" at the time when the level of a returns to "1", the levels of the first collector 201a and the second collector 201b of the transistor 201 will change one after another. Shifts to “0”.

On the other hand, immediately after time _t11 , the level of the second collector 202b of the transistor 202 shifts from "1" to "0", but this causes the first collector 301a, the second collector 301b, and the The level of the third collector 301c shifts to "1" one after another, and the transistor 301
By shifting the level of the first collector 301a of the transistor 302 to "1", the first collector 3 of the transistor 302
02a, the second collector 302b, the third collector 302c, and the fourth collector 302d transition to "0" one after another.

the third collector 302 of the transistor 302;
When the level of c shifts to "0", the level of the first collector 304a of the transistor 304 shifts to "1", and the levels of the second collector 304b and third collector 304c also shift to "1" one after another. Transition.

a second collector 304 of the transistor 304;
When the level of b shifts to "1", the levels of the first collector 305a and second collector 305b of the transistor 305 successively shift to "0", and the level of the second collector 30 of the transistor 305 shifts to "0".
As the level of transistor 5b shifts to "0", the output level of the transistor 302 returns to "1", and further the output level of the transistor 301 shifts to "0".

By the way, at time _t12 in FIG. 5, the timing at which the level of the fourth collector 202d of the transistor 202 returns to "1" and the timing at which the level of the second collector 201b of the transistor 201 returns to "1" coincide. There is a good possibility that the time at which the output level of the transistor 201 becomes "0" is slightly delayed due to subtle variations in wiring capacitance and transistor characteristics.

Therefore, when the output level of the transistor 206 is not applied to the base of the transistor 203, the output level of the transistor 203 changes immediately after the output level of the transistor 202 shifts to "1".
However, in the configuration of the present invention, the output level of the first collector 206a of the transistor 206 shifts to " ₀ " (causing a malfunction). Since the output level of the transistor 203 is prohibited from becoming "0" during the period in which the level is "0", there is no risk of malfunction.

Additionally, by similarly applying (feeding back) the output of the next stage circuit to the base of the transistor 306 constituting the unit stage 300, malfunction of the transistor 303 can be prevented.

Note that in the unit stage 200, the fact that the first collector 202a of the transistor 202 is connected to the base of the transistor 201 creates a risk of such a malfunction (by making the connection, the first collector 202a of the transistor 201 is connected to the base of the transistor 201). (The output level becomes "0" after the output level of the transistor 202 returns to "1").There is another reason for the connection.

That is, the output signal appearing at the second collector 202b of the transistor 202 is supplied to the next stage as a drive signal, but if the connection is not made, the leading edge and trailing edge of the output signal of the transistor 202 are Both edges are regulated by the leading edge and trailing edge of the input trigger signal, making it impossible to supply a drive signal with a pulse width wider than the pulse width of the input trigger signal to the next stage.

As the trigger signal propagates through many unit stages in this state, the pulse width gradually becomes narrower due to wiring capacitance, load capacitance, etc., and eventually disappears.

In the circuit shown in FIG. 4, for example, to explain the unit stage 200, the transistor 202
By connecting the first collector 202a of the unit stage to the base of the transistor 201, at least the trailing edge of the drive signal supplied to the next stage is not restricted by the trailing edge of the input trigger signal, but the trailing edge of each transistor in the unit stage is In other words, even if the pulse width of the input trigger signal becomes extremely narrow, it is possible to widen the pulse width again within the unit stage and supply it to the next stage. The trigger signal will not disappear midway.

Now, at time _t13 , the leading edge of the input trigger signal arrives, and the transistor 201
When the base level of the transistor 201 shifts to "0", the levels of the first collector 201a and the second collector 201b of the transistor 201 shift to "1",
At that point, the fourth collector 202d of the transistor 202, the third collector 2 of the transistor 204
Since the level of the first collector 206a of the transistor 206 is all "1", the output level of the transistor 203 shifts to "0", and the levels of the first collector 203a and the second collector 203b of the transistor 206 shift to "0". will shift to "0" one after another.

the first collector 203 of the transistor 203;
When the level of a shifts to "0", the output level of the transistor 205 shifts to "1", then the output level of the transistor 204 shifts to "0", and as a result, the output level of the transistor 203 shifts to "1". ” Return to

At time _t14 , when the trailing edge of the input trigger signal arrives, the output level of transistor 201 shifts to "0".

At time _t15 , when the leading edge of the input trigger signal arrives, unit stage 200 operates in the same manner as at time _t11 , and transistor 2
02 supplies a drive signal to the next unit stage 300.

a second collector 202 of the transistor 202;
When the level of b shifts to "0", the output level of transistor 301 shifts to "1", then the output level of transistor 303 shifts to "0", and then the output level of transistor 305 shifts to "1". As a result, the output level of transistor 304 shifts to "0".

the third collector 304 of the transistor 304;
When the level of c shifts to "0", the output level of the transistor 303 returns to "1", and then the output level of the transistor 301 shifts to "0", and the series of operations ends.

At time _t16 , the second
At the same time as the level of the collector 201b shifts to "0", the fourth collector 20 of the transistor 202
2d has shifted to "1", but the unit stage 200 will not malfunction in this case as well, since the B period is the period in which the output level of the transistor 203 is prohibited from changing by the transistor 206.

Now, the binary counter of the present invention shown in FIG. 4 can be configured with 6 elements per unit stage, compared to the conventional I ² L counter (flip-flop) which required 7 elements per unit stage. , the counter can be configured with a smaller number of elements.

Furthermore, when configuring a ripple counter as shown in FIG. 1, as is clear from FIG.
Since the input trigger signal is supplied to the next unit stage through two transistors, the output propagation delay between the unit stages of the counter is smaller than before.

Incidentally, in the conventional I ² L counter, the input trigger signal is supplied to the next unit stage through three transistors.

In the embodiment shown in FIG. 1, each unit stage is constructed mainly of NAND gates, but it goes without saying that the same operation is possible even if other matching gates such as NOR gates are substituted. stomach.

Effects of the Invention As is clear from the above description, in its logical configuration, the binary counter of the present invention has a first input terminal and an output terminal connected to each other in a cross-coupled manner. 1 gate pair 211, the first input terminal and the output terminal of each are cross-coupled, and the output of the first coincidence gate and the output of the second coincidence gate are supplied to the second input terminals, respectively. The third
and the second gate pair 2 by the fourth matching gate
12, a trigger signal from the previous stage is supplied to a first input terminal, an output of the first coincidence gate is supplied to a second input terminal, and the output is transmitted to the first and second coincidence gates. a fifth matching gate 25 for supplying the output of said second pair of gates to a third input terminal of said first and second matching gate (the embodiment of FIG. 1); Then, the first coincidence gate 21 and the second coincidence gate 22
A third coincidence gate 23 and a fourth coincidence gate 2 constituting a second gate pair 212 are connected to the third input terminal of the
4), a means for supplying the output of the first coincidence gate as a trigger signal to the next stage, and a fourth input terminal of the second coincidence gate to the unit of the next stage. A unit stage is constructed by a means for supplying the output of the fifth coincidence gate constituting the stage (in the embodiment shown in FIG. 1, a connection through an inverter 26), and a plurality of unit stages are connected in cascade. Because of its unique characteristics, it is possible to configure a unit stage with fewer elements and fewer wires than before, and as a result, it has great effects such as reducing IC chip size and power consumption. play.

[Brief explanation of drawings]

FIG. 1 is a logical configuration diagram of a binary counter in an embodiment of the present invention, FIG. 2 is a circuit connection diagram in which the unit stage 100 of FIG. 1 is configured with an I ² L circuit,
Fig. 3 is an operation waveform diagram of the circuit shown in Fig. 2, Fig. 4 is a circuit connection diagram in which the unit stages 200 and 300 of Fig. 1 are configured with an I ² L circuit, and Fig. 5 is an operation of the circuit shown in Fig. 4. FIG. 100, 200, 300, 400... unit stage, 211, 212... gate pair.

Claims (1)

[Claims] 1. A first gate pair consisting of first and second matching gates whose respective first input terminals and output terminals are cross-coupled connected, and their respective first input terminals and output terminals. a second gate pair of third and fourth coincidence gates connected in a cross-coupling manner and having second input terminals supplied with the output of the first coincidence gate and the output of the second coincidence gate, respectively; , a first input terminal is supplied with a trigger signal from the previous stage, a second input terminal is supplied with the output of the first coincidence gate, and the output is applied to the second of the first and second coincidence gates. a fifth coincidence gate for supplying an input terminal; means for supplying the output of said second pair of gates to a third input terminal of said first and second coincidence gates; and an output of said first coincidence gate. a unit stage by means for supplying a trigger signal to the next stage, and means for supplying an output of a fifth coincidence gate constituting the next unit stage to a fourth input terminal of the second coincidence gate. A binary counter consisting of multiple unit stages connected in cascade. 2. Claim 1, characterized in that an inverter is connected between the fourth input terminal of the second coincidence gate and the input terminal of the fifth coincidence gate constituting the next unit stage. binary counter.