JPH01197840A - Information processor - Google Patents

Abstract

PURPOSE:To execute the processing of information at higher speed by executing an arithmetic operation in parallel, when the succeeding instruction cannot refer to the result of operation of a preceding instruction. CONSTITUTION:The title processor is provided with a first counting means 24 when the succeeding instruction does not refer to the result of operation of the preceding instruction, and a store buffer 31 storing the result of operation by the arithmetic mechanism. Also, said processor is provided with a second counting means 23 counting the write to an arithmetic register 9 of the result of operation by the arithmetic mechanism, and means 1-8 for receiving the output of the first counting means at the time of starting the operation and holding its output at every arithmetic mechanism. In this state, when the succeeding instruction does not refer to the result of operation of the preceding instruction, the operation is executed in parallel. In such a way, the processing of information can be executed at high speed.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to an information processing device, and in particular a plurality of different calculation mechanisms, an instruction control mechanism, and whether or not a subsequent instruction refers to the operation result of a preceding instruction. An information processing device having means for indicating.

[Conventional technology]

Conventionally, in this type of information processing device, an instruction word and control information read by the instruction word are sent to an instruction control mechanism, and the instruction control mechanism controls the stages of each arithmetic mechanism to execute an operation.

FIG. 3 is a configuration diagram showing an example of the information processing apparatus described above, and FIG. 4 is a timing chart when instructions are executed in the order of multiplication, addition, addition, and multiplication in the configuration shown in FIG. 3.

This information processing device includes an E stage register 1.2, left digit shifters 12 and 13, right digit shifters 14 and 15, an addition circuit 16, an N stage register 5, a normalization shifter 20,
An addition mechanism consisting of an S stage register 7, an E stage register 3, 4, a multiplication circuit 17.3 a manual addition circuit 18,
Adder circuit 19, N stage register 6, normalization shifter 21. A multiplication mechanism consisting of an S stage register 8, a scientific operation register 9, an IRIO, a RAMII,
The control circuit 39, the instruction word held in the lR10, and the control information read out from the RAM 11 by the instruction word, control the E stage registers 1, 2, 3, 4, the N stage registers 5, 6, the S stage registers 7, . 8 and an instruction control mechanism 22 that controls the scientific operation register 9 using a control signal path.

Next, the operation of this conventional example will be explained.

However, it is assumed that the multiplication instruction and addition instruction used here require 5 machine cycles and 2 machine cycles, respectively. First, an instruction word of a multiplication instruction is held in IRIO, and control information in RAMII is read by the instruction word. The instruction word held in lR10 and the control information in RAMII read by the instruction word are sent to the instruction control mechanism 22. The command control mechanism 22 uses the received command and control information to determine time 1. Set data in registers 3.4 of the multiplication mechanism and start calculation. Since this multiplication instruction requires 5 machine cycles, the operation is performed in the E stage, and after 5 machine cycles, time t2
Then, the process moves to the next N stage. At the same time as the multiplication instruction moves to the N stage, the addition instruction starts executing the operation at the E stage of the addition mechanism in the same way as the multiplication instruction. Next, in the N stage, the data of the multiplication instruction is normalized by the normalization shifter 20, and the normalized data is written to the register 8 at time t3, and written to the scientific operation register 9 at time t4 one machine cycle later. It will be done. Furthermore, since the addition instruction requires two machine cycles, the operation is performed in the E stage, and the processing shifts to the next N stage at time t4 after two machine cycles.

Also, at the same time that the first addition instruction moves to the N stage processing, the second addition instruction is transferred to the E stage of the addition mechanism.
Start execution. Also, the first addition instruction is at time t
4, the normalized data is normalized by the normalization shifter 20 in the N stage, and the normalized data is written to the register 7 at time t5, and written to the scientific operation register 9 at time t6 one machine cycle later. Thereafter, multiplication and addition operations are sequentially performed in the same manner.

[Problem to be solved by the invention]

The conventional information processing device described above does not have a control mechanism for executing operations in parallel using a plurality of different operation mechanisms, and therefore has the disadvantage that it cannot execute operations at a higher speed. be.

[Means for solving problems]

The information processing device of the present invention includes a count value holding means provided corresponding to each calculation mechanism, and a count value holding means for counting the calculation start signal of the calculation mechanism and storing the count value of the calculation mechanism of the calculation start signal. a store buffer in which the calculation result of the calculation mechanism is stored; and a second counting unit whose initial value is the same as that of the first counting unit and which counts the write signal of the calculation result to the calculation register. counting means, and when the subsequent instruction does not refer to the operation result of the preceding instruction,
When the arithmetic operations of a plurality of instructions are executed in parallel using the plurality of independent arithmetic mechanisms, and the arithmetic instruction moves to the final stage, the count value holding means corresponds to the count value having the same content as the count value of the second counting means. The calculation result of the calculation instruction to be executed is written to the calculation register, and the calculation result of other calculation instructions is stored in the address indicated by the contents of the count value holding means of the calculation instruction in question in the store buffer, and when the calculation instruction moves to the final stage. Also, if there is no arithmetic instruction for which the contents of the count value holding means are the same as the count value of the second count means, the contents of the address indicated by the contents of the second count means of the store buffer are written to the arithmetic register. control means.

[For production]

Therefore, by executing operations in parallel when the subsequent instruction does not refer to the operation result of the preceding instruction, information can be processed more quickly.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an information processing apparatus of the present invention, and FIG. 2 is a timing chart when instructions are executed in the order of multiplication, addition, addition, and multiplication in this embodiment.

In this embodiment, the calculation start signal counter 24 has an initial value of 0 and counts the calculation start signals of each calculation mechanism, and the calculation start signal counter 24 has an initial value of 0 and counts up every time a calculation result is written to the scientific calculation register 9. a register 25.2 that is provided in the addition mechanism and holds the count value of the calculation start signal counter 24;
7.29, and registers 26, 28, and 30 provided in the multiplication mechanism and holding the count value of the calculation start signal counter 24.
, a store buffer 3I in which the calculation result is stored, and a selector 35 that selects the calculation result in register 7 or 8;
Select register 7 or operation result and store buffer 3
a selector 36 that selects the count value of register 29 or 30 and outputs it as a write address of store buffer 31; and registers 29 and 3.
Comparing the size of the count value of 0, selectors 34 and 35
．． and a comparator 37 that compares the count value of the software resource update signal counter 23 with the count values of the registers 29 and 30, respectively.
．． 33 and an OR gate 38 which receives the outputs of the comparators 37 and 33, selects the output of the selector 35 or the store buffer 31, and writes the selected output to the scientific operation register 9 are added to the conventional example shown in FIG.

Next, the operation of this embodiment will be explained with reference to FIG. 2, taking as an example the case where instructions are executed in the order of multiplication, addition, addition, and multiplication. First, the instruction word of the multiplication instruction is set in IRIO,
The control information in RAMII is read by the instruction word,
It is sent to the command control mechanism 22 together with the command word. The instruction control mechanism 22 receives the instruction word from IRIO and the control information from RAMII, issues an instruction to start an operation using the multiplication mechanism, and at the same time sends an operation start signal counter 24 in the instruction control mechanism 22 to the multiplication mechanism operation number holding register 26. Operation number r000J is sent. The multiplication mechanism receives an operation start instruction signal from the instruction control mechanism 22 and starts operation at the E stage (time 1+). Next, the instruction word for the addition instruction is set in IRIO one machine cycle later than the multiplication instruction, and the control information in RAMII is read from this instruction word and sent to the instruction control mechanism 22 together with the instruction word. The instruction control mechanism 22 receives instruction words from IRIO and RAMII.
When receiving the control information from the control circuit 39, it receives from the control circuit 39 whether or not this addition instruction refers to the operation result of the preceding multiplication instruction, and confirms that the addition instruction does not refer to the operation result of the preceding multiplication instruction; Start the operation using the addition mechanism. Also, at this time, the operation number r001J is sent from the counter 24 and set in the register 25, similar to the multiplication instruction. In this embodiment, a multiplication instruction of 5 machine cycle instructions and an addition instruction of 2 machine cycle instructions are used as an example. (time tz). Execution of addition instruction operation is performed in N stage register 5
At the same time as the operation number r001 of the addition instruction is set to
J is also set in the N stage register 7. Further, when the execution of the operation of the addition instruction slowly moves to the N stage, the next addition instruction, which is the third instruction, starts the operation at the E stage of the addition mechanism. Furthermore, after one machine cycle, the addition instruction, which is the second instruction that has completed normalization in N stages, moves to the next stage.

In the S stage, the operation number r0 of the second addition instruction
01 J and the contents of the software resource update signal counter 23 in the instruction control mechanism 22 are compared by a comparator 37. The counter 23 is initially set to rooo J, and since the comparison result does not match, the calculation result of the second instruction, the addition instruction, is not updated in the scientific operation register 9, but is stored in the store buffer 31 that stores the calculation result. rool" address (time ta). Next, the multiplication instruction, which is the first instruction, performs an operation in the E stage for 5 machine cycles, and then shifts the processing to the N stage for normalization. At the same time as the first multiplication instruction moves to processing at the N stage, the fourth instruction, the multiplication instruction, starts calculation at the E stage. Further, at this time, the processing is transferred to the N stage for normalization of the addition instruction, which is the third instruction, in the addition mechanism. Next, after one machine cycle, the processing of the first multiplication instruction and the third addition instruction, which have been normalized, are simultaneously transferred to the S stage for writing. Here, the operation number of the multiplication instruction and the operation number of the addition instruction are compared in magnitude by the comparator 32, and the operation result of the multiplication instruction with the smaller operation number is selected by the selector 35 and written into the scientific operation register 9. Further, the operation result of the addition instruction with the larger operation number is selected by the selector 36 and written to the roto J address of the store buffer 31. Further, each operation number is compared with the contents of the software resource update signal counter 23 by comparators 37 and 33. counter 2
Since 3 is the initial value r000J, it matches the operation number of the multiplication instruction, and it is difficult to determine whether the write to the scientific operation register 9 via the OR gate 38 is from the S stage register 8 or from the store buffer 31. determine whether
Select the output from S stage register 8.

Further, the counter 23 is incremented by ◆1 at the same timing as the update of the scientific operation register 9. In addition, in the next machine cycle, the operation number of the multiplication mechanism and the operation number of the addition mechanism do not match the contents of the counter 23, so the roll J address of the store buffer 31 read out by the contents of the counter 23, roll J. The operation result of the addition instruction, which is the second instruction, stored in is written to the scientific operation register 9. As described above, the operation results of the subsequent addition and multiplication instructions are sequentially written into the scientific operation register 9, and the instruction processing is completed.

(Effects of the Invention) As explained above, the present invention provides a first counting means for counting the calculation start signal of the calculation mechanism when the subsequent instruction does not refer to the calculation result of the preceding instruction; a store buffer for storing the calculation results, a second counting means for counting the writing of the calculation result in the calculation mechanism to the calculation register, and receiving the output of the first counting means at the start of the calculation, and holding the output for each calculation mechanism. By executing operations in parallel when the subsequent instruction does not refer to the operation result of the preceding instruction, information can be processed at a higher speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of an information processing apparatus of the present invention, FIG. 2 is a timing chart of calculation execution in this embodiment, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a block diagram of a conventional example. It is a timing chart of calculation execution in a conventional example. 1.2-... Addition mechanism E stage register, 3.4-...
- Multiplying mechanism E stage register, 5... Adding mechanism N stage register, 6... Multiplying mechanism N stage register, 7-- Adding mechanism S stage register, 8... Multiplying mechanism S stage register, 9... Scientific operation register, 10--Instruction register, 11-RAM. 12, 13--Left digit shifter, 14, 15--Right digit shifter, 16--Addition circuit, 17--Multiplication circuit, 18-3 Manual addition circuit, 19--Addition circuit, 20, 21--Normalization shifter, 22--Instruction control mechanism, 23--Software resource update signal counter, 24--Computation start signal counter, 25, 26.27.28°31--Store Buffer, 32, 33.37--Comparator, 34, 35.36--Selector, 38--OR gate, 39--Control circuit.

Claims (1)

[Scope of Claims] In an information processing device having a plurality of independent arithmetic mechanisms, an instruction control mechanism, and means for indicating whether or not a subsequent instruction refers to the arithmetic result of a preceding instruction, an information processing device corresponding to each arithmetic mechanism is provided. a first counting means for counting the calculation start signal of the calculation mechanism and outputting the count value to the count value holding means of the calculation mechanism for the calculation start signal; a store buffer in which the result of the operation is stored; a second count means whose initial value is the same as that of the first count means and which counts the write signal of the operation result to the operation register; If you don't want to see the results,
When the arithmetic operations of a plurality of instructions are executed in parallel using the plurality of independent arithmetic mechanisms, and the arithmetic instruction moves to the final stage, the count value holding means corresponds to the count value having the same content as the count value of the second counting means. The calculation result of the calculation instruction to be executed is written to the calculation register, and the calculation result of other calculation instructions is stored in the address indicated by the contents of the count value holding means of the calculation instruction in question in the store buffer, and when the calculation instruction moves to the final stage. Also, if there is no arithmetic instruction for which the contents of the count value holding means are the same as the count value of the second count means, the contents of the address indicated by the contents of the second count means of the store buffer are written to the arithmetic register. 1. An information processing device comprising: