JPH01197856A - Memory access managing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a memory access management method, particularly regarding a method of controlling access to a main storage device using a BUSY-FF method, the present invention provides a method for managing access to a main storage device using a BUSY-FF method with a simple configuration. The purpose is to perform the reset optimally during the busy time specific to the access request, and the main &! a storage device, and an access management unit that manages access requests from a plurality of processing units to the main storage device for each predetermined division unit of the main storage device, and the main storage device is currently in a busy state after the access request has been granted. A main memory control unit that sets the area in the access management section corresponding to the storage area in the access management unit as busy, and a main memory control unit that is provided for each division unit and transmits an address signal related to a permitted access request at least in a manner specific to the access management concerned. A system comprising: a pipeline that outputs a signal for resetting the busy-on area in the access management section after shifting the busy time; When reset signals output from the lines conflict, a selection circuit is provided that selects only the reset signal with the longer busy time in the pipeline, and shifts the address signal related to the unselected reset signal to the next stage. It is the composition.

[Industrial application field]

TECHNICAL FIELD The present invention relates to a memory access management system, and in particular,
The present invention relates to a method for performing i+i access management using the BUSY-FF method.

Data processing systems such as combi-tar systems are usually
It is equipped with a large-capacity main memory. This main memory is accessed by multiple processing units (terminals) within the system. Therefore, when there are multiple access requests at the same time (per unit machine cycle), it is necessary to control the contention of access requests.

[Conventional technology]

Various methods for controlling this access request conflict have been proposed in the past. Among these, the BUSY-FF method is one of the widely used control methods. BLISY-
The FF method has a memory that manages access requests from multiple processing units to the main storage device for each division of the main storage device. A main 2 It II m unit is used to busy-on the corresponding area in memory. This memory is especially BUSY-FF (busy-FF)
The busy FF corresponding to the storage area of the main storage device that is currently busy (in use) is set, and the area that is not busy is reset. Main memory t
When there is an access request from the processing device to the main storage device, the Illm unit refers to the busy-F'F and checks the busy-FF corresponding to the storage area of the main storage device to which the access request was made.

If the busy FF is set, this storage area is considered to be in a busy state and access requests are not permitted.

Conversely, if the busy FF has been reset, this storage area is deemed not to be in a busy state and the access request is permitted. In this case, if there are two or more access requests,
The main memory tsm unit grants only one access request according to a predetermined priority order.

Access requests have busy times that are unique to the access request. Therefore, after the access request is granted and a predetermined busy-Hra has elapsed, the busy-FF must be reset to return the corresponding storage area of the main storage device to a usable state again. For this purpose, traditional busy
The FF method uses a pipeline consisting of shift registers.

Once the access request is granted, the owner 21!
Addresses of 11 storage areas are input into the pipeline. This address is propagated one by one through the pipeline every machine cycle of the system6.For example, if the busy time of a certain access request is 10τ (τ is 1 machine cycle), the address associated with this access request is After being transferred in the pipeline for a short time (10τ), it is taken out from the pipeline as a reset signal for resetting the busy-FF related to this access request.

This pipeline is provided for each division unit, corresponding to the fact that the main memory is organized for each predetermined division unit. For example, when the main memory is divided into four, four pipelines are prepared.

As mentioned above, the busy time has a value specific to the access request. For example, fetch and partial store have different busy times. Therefore, two or more reset signals may be output from one pipeline at the same time. In this case, there is a method of supplying all two or more reset signals to the busy-FF, and a method of supplying only one reset signal to the busy-FF. In the former method, signal lines are drawn out from each stage of the pipeline and logically connected to the busy-FF. In the method described later, a signal line is drawn out from the stage of the pipeline corresponding to the longest busy time and connected to the busy FF.

[Problem that the invention seeks to solve]

However, conventional memory access management methods have the following problems.

Pull out the signal line from each stage of the pipeline and connect the busy-F
The memory access management system configured to connect to F has a problem in that the number of signal lines becomes enormous.

In addition, a memory access management method in which a signal line is drawn out from the pipeline stage corresponding to a long busy time and connected to a busy FF outputs all reset signals according to the longest busy time. Therefore, there is a vJm point in which the reset state is held longer than necessary, reducing the usage efficiency of the main storage device.

Therefore, the present invention solves the above problems and has a simple configuration.
It is an object of the present invention to optimally reset the busy status of a main storage device at a busy time specific to an access request.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

The main storage device 10 is divided into module units (bus units) (in the illustrated example, it is divided into four).

The main memory control unit 2o includes a plurality of processing devices 30° to 30
7-access IFJ that manages access requests from x to the main storage device 1o in each division unit! I! Parts 21a to 213
(busy-FF), the access request has been granted, and the main memory is currently in the busy state! ! The area in the access management sections 210 to 211 (for example, the area Mb of the access management section 21o) corresponding to the storage area No. 10 (for example, Ma) is set to be busy. The main memory IJIII unit 20 has branches 118 200 to 23j and a network 23, and controls conflicting access requests from the processing devices 30o to 303 according to a predetermined priority order, and connects these and the main memory 210. Connect logically.

The pipeline 40 consists of pipelines 400 to 401 provided for each division unit. Each pipeline 4
00 to 40x indicates an address signal related to an authorized access request, at least a busy signal specific to the access request.
After being delayed by a certain amount of time, it is output as a reset signal for resetting the busy-on area of the access management units 21o to 21o (for example, the above-mentioned Mb).

Selection circuits 500 to 5 (h is each pipeline 400 to 40
When the reset signals output from each pipeline conflict, the busy signal in the pipeline is
Select only the reset signal with the longer time. and,
Address signals related to unselected reset signals are shifted to the next stage.

[Effect]

The main memory 11Jtll unit 20 is the processing device 300-3
When there is an access request from 0g, the access management section 21
o to 21g, the main storage device 1 related to the access request.
Access pipe 3I corresponding to storage area 0! Part 21o~2
Check whether the area 1z is busy (set state) or not (reset state). If the main memory control unit 20 is busy, the main memory control unit 20 does not permit the access request, and if the main memory control unit 20 is not busy, it permits the access request and sets the area related to the access request from the access management units 21o to 213 to busy. (set state).

This source is simultaneously stored in the same memory lN11 from multiple processing devices!
When there is an access request, the main memory control unit 20 grants only one access request in accordance with a predetermined priority order.

For example, when an access request to the storage area Ma of the main memory wave M10 is permitted, the main storage control unit 20 sends the address of the storage area Ma to the main storage device 10, and the access management unit 21o corresponding to the storage area Ma. The area (busy-FF) Mb is set to busy-on (set state), and the above address is input to the pipeline 400 of the corresponding division unit and shifted every machine cycle (τ).

Each pipeline 400 to 401 outputs an address as a reset signal from each stage of 10τ to 12τ. Here, addresses associated with access requests with busy times of 10τ and 11τ are shifted through the pipeline 400, and simultaneously at a certain time, a reset signal associated with an access request with a busy time of 10τ is transmitted to the 10τ stage of the pipeline 400. Assume that a reset signal related to an access request with a busy time of 11τ is output from a stage of the pipeline 400. These competing reset signals are supplied to selection circuit 50o corresponding to pipeline 400.

The selection circuit 50o checks these reset signals,
Only the reset signal with the longer busy time is selected.

In the above example, the reset signal output from the 11τ stage of pipeline 400 is selected. The selected reset signal is sent to the access management section 21 of the main memory control unit 20.
o to 21m, and resets the busy-on state of the area associated with the address specified by this reset signal. On the other hand, the unselected reset signals are sent to the next stage, taken out from the pipeline 400 again in the next machine cycle, and processed in the same way.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram of the main parts of an embodiment of the present invention.

The circuit shown is the last three stages (10
τ to 12τ) and corresponds to the internal circuit of the selection circuit 50°.

The pipeline 400 is composed of shift registers, and each stage of the shift register has a valid bit V1 address ADR8,
Operation code (hereinafter simply referred to as opcode)
Stores OP and parity bit P. Valid bit (2) is "1" until address ADR8 is selected as a reset signal, and once selected, it is set to #OH. The address ADR8 is a lower address among the addresses given to the main memory device 10 from the main memory control unit 20 in FIG. OP indicates the busy time of the access request. Parity bit P is information for error correction.

The shift registers 60a and 60b include a decoder (DEC) 61a that decodes the operation code OP.

61b is connected. The outputs of decoders 61a and 61b are respectively supplied to one input of AND gates 62a and 62b. The other inputs of the AND gates 62a and 62b are provided with shift registers eoa and 6o, respectively.
The valid bit V read from b is supplied. The outputs of AND gates 62a and 62b are each supplied to a priority circuit 70. Final stage shift register 60
The valid bit V read from G is directly supplied to the priority circuit.

The priority circuit 70 and the selector 71 constitute the selection circuit 50o shown in FIG.

The priority circuit 70 is a decoder 61a.

61b and the valid bit V of the shift register 60C, the address ADR3 with the longest busy time is determined. Then, depending on the determination result, three reset enable signals RI'SET ENAI3LEA, RESE
T ENABLE B and RESEED ENABLE C
Set the level of These reset enable signals are supplied to selector 71. In addition, reset enable signals RESET l:NABLE^ and RES[
T ENABLE B is inverted and supplied to AND gates 63a and 63b, respectively. 7nd gate 63
The other inputs of a and 63b are supplied with the valid bit V read out from the shift registers 60a and 60b, respectively. Furthermore, the outputs of AND gates 63a and 63b are supplied to shift registers 60b and 60c, respectively.

Next, the operation of this embodiment will be explained.

First, the operation code OP read from the shift registers 60a and 60b is sent to the decoders 61a and 61b.
and the respective busy times r1 are determined. Now, assuming that the valid bit V of each of the shift registers 60a and 60b is "1", that is, that each 7-dress ADR8 is not selected yet, the outputs of the decoders 61a and 61b are outputted from the AND gate 62a, respectively.
and 62b, and is supplied to the priority circuit 70. Further, the valid bit V of the final stage shift register 60c is outputted to the priority circuit 70 as is. The priority circuit 70 is a shift register 60C
If the valid bit ■ from
In order to select address ADR3 stored in 0c as a reset signal, the RESET ENABLE C signal is set to high level, and the rest are set to low level.

On the contrary, if the valid bit V from the shift register 60c is 0'', that is, if the address ADR8 of the shift register 60c has already been selected as the reset signal, the output signals of the decoders 61a and 61b are checked.

Here, the decoder 61a connected to the shift register 60a with a delay time of 10τ assumes that when the decoded operation code OP indicates a busy time of 10τ or more, the access request related to this can be reset. Outputs high level. Further, the decoder 61b connected to the shift register 60b with a delay time of 11τ is
When the decoded operation code OP indicates a busy time of 11τ or more, it is assumed that the related access request can be reset, and a high level is output.

The priority circuit 70 receiving the outputs of these decoders 61a and 61b selects the one with the longer busy time if both outputs are at high level. That is, in order to select address ADR8 of shift register 60b, priority circuit 70 performs RESET EN
Only the ABLE B signal is set to high level, and the rest are set to low level. Further, if only the output of one of the decoders is at a high level, the priority circuit 7G selects the corresponding address ADR8.

The reset signal whose level has been set in this manner is sent to the selector 71, and the address ADR corresponding to the high level is
Only 8 is selected. The corresponding access pipe JI of the access management units 21o to 213 of the main memory control unit 20! The busy-on state of the area specified by the selected address ADR8 is reset. Reset enable signal RESET from priority circuit 70
ENABLE B and RESET ENABLE C
are inverted to form the seventh gate 63a and 63b, respectively.
is supplied to In this case, when address ADR8 of shift register 60a is selected, RESET ENA
Since the BLE norr signal reaches the hello level, the AND gate 63b prevents the transfer of the valid bit (■) of the shift register 60b. As a result, the valid bit V of the shift register 60c is set to "0". That is, the address ADR8 of the shift register 60c newly indicates that it is already the selected flow. Also, in the above case, RESETEN
Since the ABLE^ signal becomes high level, the AND gate 63a passes the valid bit V"1" of the shift register 60a as it is and transfers it to the shift register 60b.

As described above, the address ADR8 of the shift register 60c at the final stage is selected with the highest priority, and at other times, the address ADR8 with the better busy time is selected,
The valid bit of unselected address ADR8 is “1”
is transferred as is to the next stage while retaining the .

By doing the above, it is possible to optimally reset the busy state of the main storage device during the busy time specific to the access request.

Although the above explanation was related to the pipeline 400, the same applies to the pipelines 400 to 403.

(Effects of the Invention) As explained above, when the reset signals output from each pipeline conflict, the busy signal in the pipeline
By providing a selection circuit that selects only the reset signal with the longer time and shifting the address signals related to the unselected reset signals to the next stage, a busy reset of the main memory device can be performed with a simple configuration. This can be done optimally at request-specific busy times.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, and FIG. 2 is a principal circuit diagram of an embodiment of the present invention. In the figure, 10 is the main memory igi. 20 is a main memory control unit, 21o to 213 are access management units, 22o to 22i are branch/llllIl units, 23 is a network, and 300 to 30g are processing IN! Device #o ~ #3.40 o
403 is a pipeline, and 50o to 503 are selection circuits. Patent applicant Fujitsu Ltd.

Claims (1)

[Claims] A main storage device (10), and an access management unit that manages access requests from a plurality of processing devices (30_0 to 30_3) to the main storage device (10) for each predetermined division unit of the main storage device. (21_0~21_3
), the main storage control unit (20) has an area in the access management unit (21_0 to 21_3) corresponding to the storage area (10) of the main storage device that is currently in the busy state after the access request has been granted, and sets the area on busy. and after shifting the address signal associated with the permitted access request provided for each division unit by at least a busy time specific to the access request, the address signal is set to busy-on in the access management unit (21_0 to 21_3). In a system equipped with pipelines (40_0 to 40_3) that output as a reset signal to reset the area that has been reset, each pipeline (40_0 to 40_3) is provided with a reset signal output from each pipeline, and the reset signal output from each pipeline is A selection circuit (50_0 to 50_
3), and shifts an address signal related to an unselected reset signal to the next stage.