JPH01199232A - Microprogram controller - Google Patents

Abstract

PURPOSE:To omit the exchange of a ROM even though this ROM has a bug or a trouble and to perform the necessary processing by using a control memory using a RAM in addition to a controller using a ROM. CONSTITUTION:When a bug is detected, the valid information is invalidated within a memory circuit for valid block information in a ROM which corresponds to a block in a ROM 2 having the bug at a system rise. Furthermore a correct block undergone the correction of bug is stored in the corresponding address of a main memory. Then a system is started and the invalidated block of the ROM 2 receives an access during the operation of the main memory, the relevant block is not carried out and the correct block undergone the correction of bug is read out of the main memory and sent to a RAM 3 for execution.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control device, and more particularly to a microprogram control storage device using a continuation-only control storage device.

Conventionally, the control storage device of this type of microprogram control device is a ROM (Read Only Memory).
) was sometimes used. This is RAM (Ran
ROM (access memory)
This is because the degree of integration is several times higher and the manufacturing cost is lower.

However, if there is a bug in the microprogram in the control storage device of such a microprogram control device, there is a drawback that the ROM must be replaced with a new ROM in which the bug has been corrected. Particularly in the early stages of development, there were many bugs, and the ROM had to be replaced frequently, which increased costs.

Furthermore, in the case of a mask ROM, there is a drawback that the period required for correction is extremely long.

An object of the present invention is to provide a microbloom control device that can continue processing without replacing the ROM even if a bug or the like occurs.

Structure of the Invention The microprogram control device of the present invention includes a first storage means having a plurality of areas in which microprograms are stored in advance, and a first storage means provided corresponding to each of the plurality of areas of the first storage means. , and flag means for indicating whether the area is valid or invalid; second storage means for storing a microprogram in the invalid area of the first storage means; The present invention is characterized by comprising a continuation selection means for reading a microprogram from a corresponding area of the first storage means and reading the microprogram from the second storage means when the flag means indicates invalidity.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a system diagram showing the configuration of an embodiment of a microprogram control device according to the present invention. In FIG. , ROM valid block information storage time 1? '& (BV)4 and RA
M internal foot 7, reply memory circuit (BAA) 5,
It is configured to include a comparison circuit 6, an address translation circuit (AT) 7, a selection circuit 8, a successive register 9, and a control circuit 10.

Address register 1 holds the address of the microprogram word to be executed and has a length of 16 bits.Therefore, the address space of the microprogram is 2'' = 64K words (■ = 1024). .

ROM2 stores microprogram words of (8) from address 0000 to IFFF address (hexadecimal).Each microprogram word in ROM2 is 8 words.
It has a length of byte (1 byte = 8 bits).

RAM 3 stores a maximum of two words of microprograms. Each microprogram word in RAMB has a length of 8 bytes and is of the same format as the microprogram in ROM2. Furthermore, a maximum of 64 arbitrary blocks (32 words x 64 = 2 words) can be stored in the RAMB, each block consisting of 32 words starting from a 32 word boundary.

The microprogram word read from the ROM 2 or RAM 3 contains the address of the next microprogram word to be executed, and the address is set in the address register 1 via the signal line 100, and the microprogram word is read out from the ROM 2 or RAM 3. Program execution order control is performed.

The ROM valid block information storage circuit 4 holds valid information indicating whether the microprogram word in the ROM 2 is valid or invalid in block units.
6 words) memory circuit.

The valid information is read out using 8 bits from the 3rd bit to the 10th bit (0 origin) of address register 1 as an address. Valid information is.

"1" indicates valid, and "0" indicates invalid.

The selection circuit 8 selects the address in the address register 1 from the ROM.
When indicating the microprogram word in 2, RO
When the valid information in the M effective block information storage circuit 4 is "1", the microprogram word read from the ROM 2 is selected and output; when it is "0", the microprogram word read from the RAMB is selected and output. do.

The successive register 9 holds the microprogram word selected by the selection circuit 8, and its output 90 controls a controlled device (not shown).

Block address storage circuit in RAM This is a 5768-bit (3 bits x 256 words) storage circuit that stores the lower 3 bits of the block address held in RAM 3 as data at the address indicated by the upper 8 bits. It is. Block block address storage circuit in RAM 5 is indexed by the address of the upper 8 bits of address register 1, and the 3 bit data is compared with the 3 bits from 8th bit to 10th bit of address register 1 by comparison circuit 6. , the comparison result 60 is sent to the control circuit 10.

If the comparison result shows a match, it indicates that the corresponding block is already held in the RAM 3, and the microprogram word in the RAMB is transferred to the read register 9 via the selection circuit 8.
is read out and executed.

On the other hand, if the comparison result shows a mismatch, address register 1
Even if the address in is either inside ROM2 or outside ROM2, when the valid information in ROM valid block information storage circuit 4 is "0", it means that the necessary block is not held in RAM3. The microprogram is then stopped, the necessary blocks are read from the main memory (not shown) and held in the RAM 3, and then the execution is resumed.

In other words, when attempting to read the microprogram word at the address in address register 1 from ROM2 or RAM B, if it is determined from the comparison result that there is no valid block containing the microprogram word in ROM2 or RAM3, - Execution of the microprogram is temporarily stopped, the block is read out from the main memory (not shown) under the control of the control circuit 10, and held in the RAM 3, and then the execution of the microprogram is resumed. Note that the necessary microprogram words are stored in the main memory at predetermined addresses.

Next, the operation when reading a necessary block from the main memory will be explained using FIGS. 2 and 3. FIG. 2 is a detailed diagram of the address conversion circuit 7, and FIG. 3 is a memory map of the main memory (not shown).

In FIG. 2, the address conversion circuit 7 has a 19-bit adder, and converts the address of the block to be held in the RAM 3, indicated by the upper 11 bits of the address register 1, to the starting address of the corresponding block on the main memory. It is something that converts. B is the base address, which is the start address of the area in the main memory where the microprogram words are stored. Also, A is the upper 11 of address register 1.
This is the address of the block to be held in RAM3 indicated by bits, and 11 bits of this address A is 256 times (
= 8 (bytes) x 32 (words)) and then added to the base address B to obtain the address C of the corresponding block on the main memory device.

In FIG. 3, 32 microprogram words of the corresponding block are successively stored in the main memory from the address position obtained by the address conversion circuit 7, with each word consisting of 8 bytes (that is, one block worth of microprogram words). ), which are sequentially read out to the RAM 3.

Note that B is a base address.

To explain in detail, the address of RAM3 is address register 1.
First, write the lower 5 bits of the address of the microprogram word that caused the successive blocks (i.e., bug, etc.) to address register 1.
The address set to "0" is set. Each time a microprogram word is stored in RAM 3 from this address in the main memory, the value in address register 1 is incremented by 1 (that is, it is read 32 times from "00000" to "rllllll"). As a result, a block of 32 words was read out under the control of the control circuit 10.

After the reading of a block to RAM3 is completed, the upper 8 bits of the address of that block are used as the address for RA.
The value of the lower 3 bits of the address of the M block block address storage circuit 5 lock is written. Then, the address of the microprogram word that caused the successive blocks is set in address register 1, and execution of the microprogram word is resumed.

Next, a description will be given of remedies when a bug is detected in the microprogram word in the ROM 2 or when a failure is detected.

First, if a bug is detected, when starting up the system, the valid information in the ROM valid block information storage circuit 4 corresponding to the block in the ROM 2 containing the bug is invalidated, that is, from "1" to "0". ), the valid information of other blocks is kept valid (that is, ``1''), and the correct block with the bug fixed is stored at the corresponding address on the main memory, and the block address in RAM is stored. The memory circuit 5 is cleared so that no valid blocks are stored in the RAMB.

Then, the system is started and the ROM2 is loaded while the device is operating.
When an invalidated block within is accessed, the block is not executed (read) as described above,
The correct block with the bug fixed is transferred from main memory to RAM.
3 and executed. After that, if that block is not erased from RAMB by reading another block, when that block is accessed again, it will not be read from the main memory but from RAM3, which will affect performance such as processing speed. There is no decline.

In addition, when the occurrence of a failure is detected, the ROM2 containing the microprogram whose failure was detected at the time of the failure occurrence is
The valid information in the ROM valid block information storage circuit 4 corresponding to the block within is made invalid, and a retry is performed from the location where the failure occurred.

When the invalidated block in the ROM 2 is accessed by this retry, the correct block is read from the main memory to the RAM 3 and executed as described above.

In other words, the present invention stores information that corresponds to each block in the ROM and indicates the validity of the block, and
Every time M is accessed, that information is referred to. If the information indicates invalidity, a valid block is read from the main memory to the RAM and executed, so that from then on the processing speed does not decrease.

In this embodiment, a RAM with a smaller storage capacity than a ROM is used, but if a RAM with the same storage capacity is used, all correct blocks can be stored in the RAM in place of invalidated blocks. After reading the block from main memory, it is transferred to ROM without slowing down the processing speed of the device.
It is clear that bugs and malfunctions can be dealt with.

Furthermore, in the present invention, if the microprogram is overlaid and executed on the RAM, it is possible to execute the microprogram that exceeds the storage capacity of the ROM without reducing the speed too much.

Fish! As explained above, the present invention provides a control storage device using RAM in addition to the control storage device using ROM, and the RO
Disable the microprogram in M block by block,
By preparing a correct block in the main memory that corresponds to the invalidated block, and reading the correct block from the main memory to the RAM and executing it when the invalidated block is accessed, bugs and failures can be avoided. Even if this happens, the process can be carried out without replacing the ROM.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing the configuration of a microprogram control device according to an embodiment of the present invention, and FIG. 2 is an address conversion circuit 7.
A detailed diagram of FIG. 3 is a memory map of the main storage device. Explanation of symbols of main parts 1...Address register 2...ROM 3...RAM 4...Valid block information storage circuit in ROM 8.
...Selection circuit

Claims (1)

[Claims] (1) A first storage means having a plurality of areas in which microprograms are stored in advance, and a first storage means provided corresponding to each of the plurality of areas of the first storage means, and whether the area is valid or invalid. a second storage means for storing a microprogram in an invalid area of the first storage means; and a second storage means for storing a microprogram in an invalid area of the first storage means; A microprogram control device characterized by comprising read selection means for reading a microprogram and reading the microprogram from the second storage means when the flag means indicates invalidity.