JPH01199439A - Semiconductor packaging structure - Google Patents

Abstract

PURPOSE:To inhibit a compressive deformation load to apply to the solder bumps, which face the side of a substrate, of semiconductor element packaging parts without damaging a high-density packaging property and to obtain a semiconductor packaging structure provided with the packaging parts, which can be easily separated and connected, by a method wherein solder bumps, which have a melting point higher than that of main connection solder bumps and have little softening property, are formed on connecting terminal parts, which face the side of the substrate and are located on the outermost periphery of each chip carrier, more than 3 pieces. CONSTITUTION:In a semiconductor packaging structure mounted with a multitude of pieces of semiconductor elements 1 through microchip carriers 2 on the same substrate 7, solder bumps 5b, which have a composition of a melting point higher than that of the composition of main connection solder bumps 6b and have little softening property, are formed on connecting terminal parts, which face the side of the substrate 7 and are located on the outermost periphery of each carrier 2, more than 3 pieces to maintain the parallelism of the elements 1 to the substrate 7. For example, more than 3 pieces of the above bumps 5b are made smaller their diameters than those of the bumps 6b. Moreover, in case the composition of the bumps 6b is set in the composition of an Sn-Pb eutectic solder (a melting point of 183-190 deg.C) bump or the like, the composition of more than 3 pieces of the bumps 5b is set in the composition of an Sn-Sb solder (a melting point of 242 deg.C or higher) bump.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a next-generation large-scale computer having a structure in which semiconductor elements are mounted on a multilayer substrate using a microchip carrier.
The present invention relates to a highly reliable mounting structure in which solder bumps that can withstand compressive deformation are formed on the microchip carrier pad portion facing the multilayer substrate.

[Conventional technology]

As described in U.S. Pat. No. 4,081,825, the conventional device is a multi-chip module structure in which a large number of semiconductor elements are mounted on a multilayer ceramic plate. It is a water-cooled system in which a housing with a water passage is bonded with solder, and sealing is done by mechanical compression using a metal gasket. [The mechanical pressure applied during sealing by screws and crimping is applied from the solder material inside the housing to the semiconductor element and the solder bumps, resulting in short circuits between adjacent solder pans 1 due to significant deformation or damage to the wiring pattern. No consideration was given to this point. In addition, if a semiconductor element is connected to a multilayer ceramic board using solder bumps, then solder foil or spherical solder is placed on top of the element, and the element is soldered to the housing after sealing with a metal gasket is completed, the back side of the element As the solder shrinks during the solidification process, a tensile force is applied to the previously attached element, which may cause the element and the wiring pattern on the multilayer ceramic board to break, or when disconnecting a large number of the elements. Consideration should be given to issues such as re-melting the solder on the back of all the elements, detaching them, and melting and connecting them again, which would have a large number of heat effects on a large number of elements, leading to deterioration of the element characteristics and damage to the element metallization. There was no.

In addition, as described in Japanese Utility Model Application Publication No. 56-78356,
At the center of the semiconductor element of the 81 wafer (consisting of multiple semiconductor element units) on which bumps for solder connection have been formed,
A control alloy having a melting point higher than that of the bump is formed, melted, and connected to the substrate control metallization, and the semiconductor element is lifted by the surface tension of the central control alloy. However, [2] In this method, a control alloy bump is formed in the center of the semiconductor element, so the semiconductor element is lifted, that is, the entire solder connection bump is lifted by surface tension, so k is a considerable volume, that is, the bond. There was no consideration given to high-density mounting structures, such as the need for a surface. Furthermore,
Because the control alloy bump has a high melting point, many other solder connection bumps will inevitably remelt when disconnecting, thus preventing the connection from shifting or melting the metallization in the solder. No consideration was given to issues such as severe deterioration of connection reliability.

[Problem to be solved by the invention]

The above conventional technology has a mechanical crimp sealing structure and a structure in which the semiconductor element is soldered to the cooling housing part, and the element solder bumps are short-circuited due to the crimp force and the damage force due to solder solidification during solder connection is caused. Disconnection of wiring pattern,
Furthermore, there are problems such as deterioration of element characteristics and damage to element metallization due to repeated thermal effects during element repair. In addition, forming a control alloy bump with a large area in the center of the connecting solder bump forming part of a semiconductor element is contrary to the direction of high-density packaging, and furthermore, when disconnecting, a control alloy bump with a high melting point composition is formed. Re-melting the semiconductor element will melt all the solder bumps on the other semiconductor elements, causing misalignment of the element and severe melting of the metallization, leading to a decrease in reliability. When a cooling structure is mounted on top of the element, the solder bumps are compressed and deformed, causing problems such as short circuits between adjacent bumps.

An object of the present invention is to suppress the compressive deformation load applied to the board-side solder bumps of the semiconductor element mounting portion mounted on the same substrate without impairing high-density packaging, and to facilitate the connection and disconnection of the mounting portion. An object of the present invention is to provide a reliable semiconductor device structure.

[Means for Solving Problem R] To summarize the present invention, the present invention relates to a semiconductor device structure, and is a semiconductor device in which a large number of semiconductor elements are mounted on the same substrate via one microchip carrier. In the packaging structure, a solder bump with a melting point higher than that of the main connection solder bump composition and less softening is applied to the connection terminal portion facing the substrate side of the microchip carrier, and a solder bump with a lower softening property is applied to the outermost connection terminal portion of the microchip carrier. The feature is that three or more parallel plates are formed to maintain parallelism with the substrate.

The purpose is to provide a solder bump with a composition having a melting point higher than that of the main connection solder bump, which has a lower softening property, and which has a lower softening property and which has a higher melting point than the main connection solder bump composition, on the same substrate, and which connects semiconductor elements with a microchip carrier using solder bumps. This is achieved by forming three or more compressive deformation suppressing solder bumps having a diameter smaller than the solder bump diameter on the outermost periphery of the connection pad portion so as to maintain parallelism with the substrate.

Semiconductor 9 in which multiple semiconductor elements are mounted in one microchip carrier structure on the same substrate! In the mounting structure,
Three or more high melting point solder bumps provided on the outermost periphery of the structure on the substrate side to maintain parallelism with the substrate,
Even when the main connecting solder bump of an adjacent structure that is not connected to the substrate metallization is melted and disconnected, it does not melt and maintains the bump shape.

Therefore, the structure to be disconnected has l! If the main connection solder bump of the structure in contact with lI$ softens due to heating during disconnection, and even if a heat sink is mounted on the structure and a compressive load is applied, the main connection solder bump will be A highly reliable structure can be maintained without being deformed by the pressure #aK and short circuiting between adjacent solder bumps. In addition, when sealing the board and cooling housing with solder, the solder bumps can be maintained by suppressing compressive deformation even when heated to near the melting temperature of the main connecting solder bump of the structure, so the selection of the sealing solder material is important. It is possible to provide a margin in the temperature range of the scorching sealing condition, and it is possible to ensure a highly reliable connection part in the overall structure.

In an embodiment of the present invention, it is preferable that the three or more solder bumps have a diameter smaller than that of the main connection solder bump. Further, it is preferable that the five or more solder bumps are on the same substrate on which the main connection solder bumps are formed, but are not connected to the substrate. The composition of the main connection solder bump is Sn −
Pb eutectic solder (melting point 183-190℃), sn
-Mg eutectic solder (A point: 221°C), the composition of the three or more solder bumps is preferably Sn-81) type solder (melting point: 242°C or higher).

〔Example〕

Hereinafter, the present invention will be explained in more detail with reference to Examples.
The present invention is not limited to these embodiments.

Note that FIGS. 1 to 3 are explanatory diagrams of embodiments of the present invention, and FIG. 4 is an explanatory diagram of a conventional example.

Embodiment 1 FIG. 1-1 is a vertical sectional view of a mounting structure in which strain suppressing bumps are formed according to an embodiment of the present invention, and FIG. 1-2 is a partially enlarged sectional view thereof, and reference numeral 1 indicates a semiconductor element. , 2 is a chip carrier, 3 is an OCR solder, 4 is a sealing resin, 5b is a strain suppression bump, 6°C is a eutectic solder bump, 7 is a multilayer module board, 8 is an input/output bin, 9 is a heat sink, 10 means housing, 11Fi sealed solder.

Multilayer module board 7 equipped with input/output pins 8 on the back side
A heat dissipation body 9 for dissipating and transmitting the heat generated by the element is attached to the back surface of the semiconductor element 1, which is connected by OOB solder 3 to a chip carrier 2 for enabling disconnection, after forming strain suppression bumps 5b in advance. Connecting eutectic solder bump 6
After forming b, the pads of the multilayer module board are aligned and connected by heating and melting b0.Furthermore, in order to cool the heat generated by the semiconductor elements, protect the characteristics of the elements, and improve reliability, the entire area where the elements are mounted is part of the housing 10 (e.g. Cu
The multilayer module board 7 is sealed with a sealing solder 11 (Mo material or 11M material).

In this case, the connection between the chip carrier 2 and the semiconductor element 1 is as follows.
The OCB solder 3 of Pb-2%sn is mounted on the multilayer module board with the main connecting eutectic solder bumps 6b, e.g.
n -4Q % Pb eutectic solder internal point: liquid phase 190℃
, solid phase 183°C) or Sn-55T Ag eutectic solder (melting point: 221°C), but the main connection eutectic solder bump 5b is used to suppress compressive deformation, that is, as the strain suppression bump 5b. Solder composition with a higher melting point than that of 6b, e.g. Sn -5% Bb solder (melting point: 242°C)
was used.

Therefore, as the substrate sealing solder 11 material of the housing, at least the melting point of the eutectic thread solder (solid phase 183° C.) is used to prevent damage such as remelting the mounting portion.
It is necessary to seal with a lower solder. Therefore, in the present invention, a low-temperature solder, for example, a solder consisting of 45% Pb, 118% B, and the remainder An, has a liquid phase temperature of 160°C and a solid state of 136°C.
) was sealed.

When sealing with low-temperature solder material, it is difficult to solder seal by heating only the sealing part because the heat capacity of the multilayer module board and cooling housing is large. The only way to do this is to do the actual heating. For this reason, main heating (sealing soldering temperature 17
5±5℃) Ilc, so the main connection solder, e.g. Sn
-401I'b eutectic solder tends to soften at that temperature. In reality, the amount of strain increases rapidly from a temperature of 176°C. Therefore, a short circuit occurs between adjacent solder bumps as shown in the solder bumps of the mounted microchip carrier on the right side shown in FIG. FIG. 4 is an explanatory diagram of a compressively deformed state of a solder bump according to a conventional method structure, and reference numeral 6C indicates a compressively deformed bump. This phenomenon does not occur during solder sealing, but can also occur when the mounted microchip carrier shown on the left side of Figure 4 is attached to and detached from the multilayer module board. reliability is in a very bad condition.

Figures 2-1 to 2-3 and Figures 6-1 to 5-3 show compression suppressing solder bumps and main connection solder bumps on the connection pads facing the multilayer board side of the microchip carrier. 2-4 and 3-4 are plan views of compression suppressed solder bumps. In each figure, 2a is a connection pad, 5 is a press-fit solder, 5
a means molten solder, 6 means press-fit eutectic solder, 6a means molten eutectic solder, 12 means solder ball carrier, and 16 means stepped solder carrier.

FIG. 2-1 shows solder bumps, such as Sn-5%Sb (@
In order to obtain the necessary amount to form a solder ball diameter of 250 μm, for example, a metal mask that does not melt and react with the solder, such as a nutless steel foil (
A solder ball carrier 12 press-fitted into a through-hole portion with a thickness of 250 μm is aligned and installed on the connection pad after applying rosin thread flux. In this case, the press-fit solder 5 in the through hole of the solder ball carrier 12
It is necessary that the amount of solder bumps on the microchip carrier 2 is smaller than the amount of the main connection solder bumps on the microchip carrier 2. The reason for this is that when mounting on a multilayer module board in a later process, the solder also wets the connection pads of the module board, and the height after connection becomes smaller than the height of the supplied solder bumps.

FIG. 2-2 shows the microchip carrier 2! /c Heating the solder ball carriers 12 in the aligned state,
In this state, the press-fit solder 5 is melted, and as a result of heating and melting, the press-fit solder 5 becomes spherical and floats on the upper surface of the solder ball carrier due to the surface tension peculiar to molten metal.

Then, as shown in FIGS. 2-3 and 2-4, the connecting pads 2aK of the microchip carrier 2 are brought into contact with each other, exhibiting solder wetting, and strain suppressing bumps 5b are formed.

In Figure 3-1, in order to form a main connection solder bump on the central pad portion of the microchip carrier, a stepped solder ball △ is processed so as not to contact the strain suppression bump 5b that has already been connected and cleaned. A rosin thread patch is applied to the carrier 15, and the carrier 15 is positioned opposite to the pad.

Difference: In this case, the △ press-fit solder 6 of the stepped solder ball carrier 13 has a solder composition with a lower melting point than the pre-formed solder bump 5b, for example Sn-40% Pb solder (
Melting point: 183 to 190° C.) 6, and the amount needs to be larger than the strain suppressing solder bump 5b for the reason mentioned above, and in this example, the amount was set to form a φ300 μm solder pole.

Figure 3-2 shows a heated state similar to the method used to form the strain suppression bumps 5b, and the press-fitted solder 6a becomes spherical, and the main connection solder bumps (eutectic solder) are formed as shown in Figure 3-3. Bumps 6b) can be formed. 3-4
The figure is a plan view of FIG. 3-3.

As shown in FIGS. 3-3 and 3-4, on one surface of the chip carrier 2, a semiconductor element mounting portion is formed with two types of strain suppression bumps 5b and main connection eutectic solder bumps 6b. It is aligned with the connection pad portion of the multilayer module board 7 and connected by heating and melting (FIG. 1).

By forming such a mounting structure, it is possible to provide leeway in process conditions such as disconnection and sealing, resulting in a highly reliable semiconductor mounting structure.

〔Effect of the invention〕

According to the present invention, compressive deformation of the high-density semiconductor solder bump mounting portion can be suppressed, so that the mounting portion can be easily disconnected and the sealing portion can be opened. Therefore, there is an effect that a highly reliable, high-density semiconductor device can be manufactured.

[Brief explanation of the drawing]

Fig. 1-1 is a longitudinal sectional view of an example of the structure of the present invention;
2 is a partially enlarged sectional view thereof, FIGS. 2-1 to 2-3 and 3-1 to 3-3 are explanatory diagrams of the bump forming method in the present invention, and FIGS. 2-4 and 5-4 is a plan view of the bump, and FIG. 4 is an explanatory diagram of a conventional example. 1: Semiconductor element, 2: Chip carrier, 2a: Connection pad, 5: OOB solder, 4: Sealing resin, 5: Press-fit solder, 5a: Molten solder, 5b = Strain suppression bump, 6:
Press-fit eutectic solder, 6a: Molten eutectic solder, 6b: Eutectic solder bump, 6C: Compression deformation bump, 7: Multilayered Joule board, 8: Input/output pin, 9: Heat sink, 10: Housing, 11: Sealing Solder stopper, 12: Solder pole carrier,
13: Solder carrier with steps

Claims (1)

[Claims] 1. In a semiconductor mounting structure in which a large number of semiconductor elements are mounted on the same substrate via a microchip carrier, a main connection is made to the connection terminal portion facing the substrate side of the microchip carrier. A semiconductor characterized in that three or more solder bumps having a melting point higher than the melting point of the solder bump composition and having less softening properties are formed on the outermost peripheral connection terminal portion of the microchip carrier to maintain parallelism with the substrate. Implementation structure. 2. The semiconductor mounting structure according to claim 1, wherein the three or more solder bumps have a diameter smaller than that of the main connection solder bump. 3. The semiconductor mounting structure according to claim 1, wherein the three or more solder bumps are not connected to the same substrate on which the main connection solder bumps are formed. 4. When the composition of the main connecting solder bumps is Sn-Pb eutectic solder (melting point 183 to 190°C) or Sn-Ag eutectic solder (melting point 221°C), the three or more solder bumps The composition of Sn-Sb solder (melting point 242
2. The semiconductor mounting structure according to claim 1, wherein the temperature is at least .degree.