JPH01200439A - Priority processing circuit for unaccepted request - Google Patents

Abstract

PURPOSE:To accept an unaccepted request with priority by masking the request received from a unit that already accepted a request and accepting and taking out only the requests having the lower ranks than that of the request accepted in the preceding time. CONSTITUTION:An input signal 31 is supplied to an AND circuit 32 which masks the requests given from the unit that is accepted the requests received up to the preceding time within a cycle out of the requests received this time and also to an AND circuit 33 which takes out only those requests having lower ranks than that of the preceding request accepted. Furthermore, the contents 35 of a 1st register 34 storing the information showing the specific units which requests are accepted down to the preceding time within a cycle are supplied to the circuit 32. In the same way, the contents 37 of a 2nd register 36 which holds the mask information for acceptance of only those requests lower than that requested in the preceding time are supplied to the register 33. In such a constitution, the requests given from the units that are not accepted down to the preceding time within a cycle can be accepted with prior ity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to priority determination control, and more particularly to an unaccepted request priority circuit that dynamically determines and controls priorities.

[Conventional technology]

As computers become faster, so-called interrupt processing, which enables the required functions to be performed at the required time, is essential for efficient computer operation. When a large number of such interrupts occur at the same time, interrupt processing is performed sequentially starting from the one with the highest priority. In this case, a priority determination circuit is used to determine the priority of interrupts.

FIG. 3 shows a conventional example of a priority determining circuit such as this, and FIG. 4 explains its operation.

Here, for the sake of simplicity, the input signal 11 is set to 4 bits. This input signal 11 is sent to a priority encoder 12 that converts 4 bits into 2 bits (4→2).
It selects and outputs the highest order bit from among the plurality of required bits in the 4-bit input signal 11.
This is the same operation as an encoder. In this conventional example,
Priorities are fixed. The output signal 13 of the priority encoder 12 encoded into 2 bits is input to a decoder 14 which decodes the 2 bits into 4 bits. This decoder 14 converts from general 2 bits to 4 bits.
It is the same as the (2→4) decoder that converts to bits. This decoder 13 provides a decoded 2-bit output signal 14.

The operation of this conventional first priority ranking determination circuit will be explained with reference to FIG. This figure is a table for determining accepted requests, and is divided into six cases (1) to (2) according to the input signal 11, that is, the type of accepted request. High→low indicates that the priority order 21 of the input terminal of the priority encoder 12 is low and fixed from left to right. The input signal 11 has a 4-bit array of 1000 in case (2), for example, and therefore the first bit with the highest priority is selected at position 22 (arrow in the table). The same applies to other cases (■) to (■).

In this way, the output signal 13 selected by the priority encoder 12 is, for example, 3 in case (2).

The output signal 13 is obtained in the same manner in other cases (1) to (2). Next, these output signals 13 are decoded into a 4-bit binary code by a decoder 14, and for example, in case (2), 1000 is obtained as the output signal 15. Other cases■〜■
The same is true in the case of , and the selected position 16 ends up being the position indicated by the arrow in the figure.

As explained above, in the conventional priority order determination circuit in which the priority order is fixed, the highest order request among a plurality of requests is selected and output.

As described above, in this type of conventional priority determination circuit, the priority is often uniquely determined by the system. If you want to change such a fixed priority, use
There are methods to change the settings when starting up the system, or to use commands, switching switches, or using ROM. Furthermore, if you want to dynamically change the order, there is also a method of periodically reversing the order from high to low.

[Problem to be solved by the invention]

However, in most of these conventional methods, the priority order is fixed, and when there are multiple requests, the high-rank requests pass frequently, but the low-rank requests pass infrequently, resulting in inefficiency. The problem is that it's bad. Another problem is that even if the priority order is changed using commands or switches, the order remains fixed during system operation. Furthermore, even when reversing the order from low to high, there is a problem in that the higher order is prioritized between reversals.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide an unaccepted request priority circuit that can preferentially accept unaccepted requests and can evenly accept collection requests.

[Means to solve the problem]

The unaccepted request priority circuit of the present invention includes a first register having an n-bit width that holds information about which unit's requests have been previously accepted within one cycle until requests from all n units are accepted at once. The content of this n-bit wide first register is ANDed with the input n-bit request signal, and it is determined whether any requests have been accepted up to the previous time within l cycles within the current request. a first AND circuit that masks a request from a certain unit; a second register with an n-bit width that holds mask information for accepting only requests lower than the previously accepted request; a second AND circuit that performs an AND operation between the contents of the second register and the input n-bit request signal, and extracts only requests lower than the previously accepted request; If the result shows that there is no request lower than the previously accepted request, the input request signal is selected, and if not, the first selector selects the output of the second AND circuit. If the output of the first AND circuit indicates that there is no request from a unit that has not been previously accepted within one cycle among the input request signals, the first selector a second selection circuit that selects the output of the first logical product circuit and, if not, selects the output of the first AND circuit, and a second selection circuit that selects the output of the first AND circuit; A priority encoder that selects and outputs the highest-ranked one from the above, a decoder that receives the output of this priority encoder and decodes it into n bits, and n bits from this decoder.
The output of the bit is logically ANDed with the contents of the first register, and only the requests lower than the request received last time are taken out. a third AND circuit that operates to update or inhibit the first register; and an exclusive link between the n-bit output of the third AND circuit and the contents of the first register. An exclusive OR circuit that operates to take a logical sum and update the first register, and the n-bit output of this exclusive OR circuit are input, and when this input is "0"', l is input. Assuming that the cycle has ended, all bits are output as “1” so that there is no mask for the next n-bit request signal, and this input is “1”.
a first comparator circuit that outputs it as is and sets it in the first register when it is not 0'', and a subtracter that subtracts 1 from the n-bit output from the decoder and updates the second register. circuit and the output from this subtraction circuit, and when this input is "0", it is assumed that l cycle has ended and all bits are "1", so that there is no mask for the next n-bit request signal, This input is “′0
and a second comparator circuit that outputs the signal as is and sets it in the second register when the signal is not ``.''.

Therefore, when the unaccepted request priority circuit according to the present invention is used, requests from units that have already accepted requests are masked, and only requests with a lower rank than the previously accepted request are accepted and taken out. Requests from units that were not accepted previously can be accepted with priority. Furthermore, it is possible to accept requests from units that have already received requests on average.

〔Example〕

The present invention will be described in detail with reference to Examples below.

FIG. 1 is a block diagram showing the unaccepted request priority circuit of this embodiment, and FIG. 2 is a diagram showing an accepted request determination table showing its operation. In this embodiment, as in the conventional example, the input is 4.
It's a bit of a bit of a bit of a bit of a bit of a bit of a bit.

In FIG. 1, the input signal 31 is as follows in the current request:
■First AND circuit 3 that masks requests from units that have received requests up to the previous cycle.
2 (hereinafter referred to as the first AND circuit) and a second AND circuit 33 (hereinafter referred to as the second AND circuit) that extracts only requests lower than the previously accepted request. The first AND circuit 32 further includes a 4-bit wide first register that holds information about which unit's request was previously accepted within one cycle until requests from all four units are accepted. The contents 35 of 34 are input. Similarly, the second AND circuit 33 further includes a 4-bit wide second register 3 that holds mask information for accepting only requests lower than the previously accepted request.
6 contents 37 are input. This second AND circuit 33
The output signal 39 of , that is, the result of ANDing the input signal 31 and the content 37 of the second register 36 is sent to the first selector 40 . Given. This first selector 40
selects the input signal 31, that is, the request signal, when the output signal 39 of the second AND circuit 33 indicates that there is no request lower in level than the previously accepted request. and,
Otherwise, the output signal 39 of this second AND circuit 33 is selected.

Selection signal 42 selected by this first selector 40
is sent to the second selector 43. Further, this second selector 43 is given an output signal 44 of the first AND circuit "I&32," that is, a request that is lower than the previously accepted request.
When the output signal 44 of the D circuit 32 indicates that among the requests of the input signal 31, there is no request from a unit that has not been previously accepted within one cycle, the first selector 4
The selection signal 42 which is the output of 0 is selected, and if not, the output signal 44 of the first AND circuit 32 is selected.

The selection signal 46 which is the output of this second selector 43 is
The signal is input to a priority encoder 48 which operates in the same way as a general 4-bit (4bit/) to 2-bit (hereinafter abbreviated as 4→2) encoder. This priority encoder 48 selects the highest order bit from among the plurality of requested bits among the 4-bit output of the second selector 43 and outputs an encoded signal 49. This code signal 49 is sent to the decoder 5
It is inputted as 0 and converted to 4 bits again to become the decoded signal 52. This decoded signal 52 can be taken out as an output signal 69, but is further outputted to a third AND circuit 5.
3 and the subtraction circuit 54.

The third AND circuit 53 connects this decoded signal 52 and the first
The content 35 of the first register from the register 34 of
In the case of a request from a unit that has been accepted up to the previous time in the cycle, the update of the first register 34 is suppressed. That is, the third AND circuit 53 is called an exclusive OR circuit 55 (hereinafter referred to as an XOR circuit).

) and sends out a 4-bit output signal 56. This XOR circuit 55 receives the output signal 5 of the third AND circuit 53.
6 and the contents of the first register from the first register 34 3
Exclusive OR with 5 is taken.

An output signal 57 from this XOR circuit 55 is sent to a first comparison circuit 58. The first comparison circuit 58 that receives this
This output signal 57 is sent to the first register 34 as "
When the output signal 57 is not "0", it outputs "1" (all pins) assuming that the cycle has ended so that there is no mask for the next 4-bit request signal, and if this output signal 57 is not "0", it outputs it as is. The subtraction circuit 54 that receives the decode signal 52 subtracts 1 from the decode signal 52 and outputs the subtraction signal 62 to the second register 34. The second comparison circuit 63 sends an inhibit/update signal 65 to the second register 36. As a result, the second register When the signal 62 is "0", all bits are "1" as the inhibition/update signal 65, so that there is no mask for the next 4-bit request signal, and when the subtraction signal 62 is not "0", This is input as is as the inhibition/update signal 65 and is set.

Next, the operation of the unaccepted request priority circuit of this embodiment will be explained with reference to FIG.

In the figure, for comparison, the 4-bit input signal 31 is
The same one as the conventional example shown in FIG. 4 will be used. It is assumed that the required position 67 of each input signal 31 is at the position indicated by the arrow in the figure. In case ■, the contents 35 and 37 of register 34 and second register 36 of ml are "
1111'', that is, there is no mask.
The AND circuit 32 calculates the content 35 of this first register.
1111" and the input signal 31 "1000", and sends "1000" as the output signal 44 to the second selector 43. As already explained, the first AND circuit 32 receives the current input signal Among the 31 requests, the operation is performed to mask requests from units that have received requests up to the previous time in the I cycle, but since this is the first time, not all bits were masked.Furthermore, The second AND circuit 33 selects the contents 37 of the second register.
“1111” and the input signal 31 “1000” are ANDed and “1000” is sent to the first selector 40 as the output signal 39. As already explained, this second AND circuit 33 also operates to accept only requests lower than the previously accepted request, but since this is the first request, all bits are permitted.

The first selector 40 selects the input signal 31 when the output signal 39 of the second AND circuit 33 is "0", that is, when there is no request lower in level than the previously accepted request among the requests of the input signal 31. , otherwise the second AND circuit 3
3 output signals 39 are selected. Therefore, in the current case, there is a lower request than the request received last time, so the output signal 39 of the second AND circuit 33, that is, "1000" is selected, and the selection signal 42 is selected.
“1000” is sent to the second selector 43.

The second selector 43 is activated when the output signal 39 of the second AND circuit 33 is "0", that is, when there is no request from a unit that has not been previously accepted within one cycle among the requests of the input signal 31. selects the selection signal 42 of the first selector 40; otherwise, the first AND circuit 32
It is configured to select the output signal 44 of. Therefore, in the current case, the output signal 4 of the first AND circuit 32
4 “1000” is selected and “100” is selected as the selection signal 46.
0'' to the priority encoder 43.

This priority encoder 48 is the same as that described in the conventional example, and the priority order 71 of its input terminals is as follows:
The high level is on the left, and the low level is on the right.The first request from the highest level of the input selection signal 4G "1000" from the second selector 43 is selected, and "3" is output as the encoded signal 49.
(This value is the encoded binary value expressed in lO base value) is sent to the decoder 50. The decoder 50 decodes this and sends "1000"' as the decoded signal 52 to the third AND circuit 53 and the subtraction circuit 54.

This decoded signal 52 can also be taken out as an output signal 69 to the outside. The selected position 72 in this case is the position indicated by the arrow in the figure. Third AND circuit 53
takes the AND of this decoded signal 52 and the content 35 of the first register which is the output of the first register 34,
“1000” is set to the XOR circuit 55 as the output signal 56.
Send to.

As already explained, the third AND circuit 53 outputs "oooo" if the request in the input signal 31 received this time is from a unit that has been received previously within one cycle. However, it operates to inhibit updating of the first register 34. In the current case, since the request was from a unit that had not been accepted before, "1000n" was output.

The XOR circuit 55 receives the output signal 5 of the third AND circuit 53.
6 “1000” and the first output which is the output of the first register 34.
Exclusive OR with the register contents 35 "1111" is performed, and "0111" is sent as the output signal 57 to the first comparator circuit 58. This XOR circuit 55 operates to update the first register 34, as described above. When the first comparison circuit 58 receives the output signal 57 of the XOR circuit 55, it checks whether it is "0000" or not. If it is "0000", one cycle has been completed, so it suppresses "1111". - Output as update signal 60, otherwise output signal 57 as input
It operates to output as is. The current case corresponds to the latter, and "0111" is output as the inhibition/update signal 60.

This is then written to the first register 34, and this first register 34 is updated.

On the other hand, the decoder signal 52 "1" sent to the subtraction circuit 54
000'' is here subtracted by 1, and sends ``0111'' as the subtraction signal 62 to the second comparison circuit 63. As already explained, this subtraction circuit 54 updates the second register 36. The second comparison circuit 63 receives the subtraction signal 62 which is the output of the subtraction circuit 54.
When this is input, it is checked whether it is "0000" or not. If it is "0000", the request received this time is the lowest request, so "'1111" is set as the output of the inhibition/update signal 65. The signal is output to the register 36 of No. 2, and if not, the signal is output as is. The current case corresponds to the latter, so "0111" is output as the inhibition/update signal 65, which is sent to the second register 3.
6 and this second register 36 is updated.

Case ■ also operates in the same way. In other words, since the first register 34 has been updated in case ■, this first register 34
The content 35 of the register is "0111'°, and the AND of this and the input signal 31 "0010" is the first A
It is taken by the ND circuit 32. In this first AND circuit 32, the third request from the highest order is not masked, so the decode signal 52 of the decoder 50 becomes "0010".
The third request from the highest level will be accepted.

The content of the first register 34 is “0101”.
”, and the contents of the second register 36 are updated to “0001”.

In case ■, the content 35 of the first register 34, which is the output of the first register 34, is "0101", and the first AN
The first request from the highest level is masked by the D circuit 32, and its output signal 44 becomes "oooo", so the second request is masked.
The selector 43 selects the selection signal 42 "1000" which is the output of the first selector 40. At this time, the content 3 of the second register which is the output of the second register 36
7 is "0001", and the second AND circuit 33 masks the first request from the highest order, so the first selector 40 selects the input signal 31 "1000", and the first selector 40 selects the input signal 31 "1000". ``1000'' is output as the selection signal 42 which is the output of . Therefore, the selection signal 46 which is the output of the second selector 43 is "1000"
becomes.

Then, "1000" is output as the decode signal 52 which is the output of the decode 50, and the first request from the highest order is accepted. In this case, the first register 34 is not updated, but the second register 36 is “0”.
111”.

Furthermore, in case (3), the content 35 of the first register 34 which is the output of the first register 34 is "0101", and the first and third requests from the highest order are masked by the first AND circuit 32. The output signal 44 of the first AND circuit 32 becomes "0000". Therefore, the second
The selector 43 selects the selection signal 42 that is the output of the first selector 40, but at this time, the content 37 of the second register that is the output of the second register 36 is “
0111''.Thus, the second AND circuit 33 masks the first request from the trial position received last time, but does not mask the third request. “0010” is output as the output, and the first selector 40 selects the second AND circuit 3.
Output signal 39, which is the output of No. 3, is selected. the result,
As the selection signal 42 which is the output of the first selector 40, “
0010" is output. As a result, the selection signal 46 which is the output of the second selector 43 is "OO10".
Therefore, “0010” is output as the decoded signal 52 which is the output of the decoder 50. Thus, the third request from the highest level will be accepted. At this time,
The first register 34 is not updated, but the second register 36 is updated to "0001".

In case (■), the content 35 of the first register 34, which is the output of the first register 34, is "0101", but
The first AND circuit 32 masks the first and third requests from the highest order, but does not mask the second request. Therefore, "0100" is output as the decode signal 52 that is the output of the decoder 50, and the second request from the highest order is accepted. and,
The first register 34 is set to 0001'', the second register 3
6 are respectively updated to '0011'''.Finally, in case 3, the content 35 of the first register 35, which is the output of the first register 34, is “0001”, and the first AND
The first, second, and third requests from the highest level are masked by the circuit 32, but the fourth request is not masked. Therefore, "0001" is output as the decode signal 52 which is the output of the decoder 50, and one cycle is completed.

Then, the output signal 57 of the XOR circuit 55 is “0000”
Therefore, the inhibit/update signal 60 which is the output of the first comparator circuit 58 becomes "1111" and is written into the first register 34. On the other hand, since the request received this time is the lowest request, the subtraction signal 62 which is the output of the subtraction circuit 54 is "0".
000'', and the inhibit/update signal 65, which is the output of the second comparison circuit 63, becomes '1111' and is written into the second register 36.

〔Effect of the invention〕

As explained above, the present invention masks requests from units that have already received requests, and accepts and extracts only requests lower than the previously accepted request, thereby making it possible to mask requests from units that have already received requests, and to accept and extract requests that are lower than the previously accepted request. This has the effect of allowing requests from previously unavailable units to be accepted on a priority basis.

Furthermore, there is an effect that requests from units that have already received requests can be accepted on average. Therefore, if the present invention is used to control the right to use the common bus, it is possible to use the bus efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the unaccepted request priority circuit according to the present invention, FIG. 2 is a diagram showing its operation in the form of an accepted request determination table, and FIG. 3 is a conventional fixed priority determination circuit. FIG. 4 is a block diagram showing the operation in the form of an acceptance request determination table. 32...First AND circuit, 33...Second AND circuit, 34...First register, 36...Second register, 40...First selector, 43...Second selector, 48...Priority encoder, 50...
... Decoder, 53 ... Third AND circuit, 54 ... Subtraction circuit, 55 ... XOR circuit, 58 ... First comparison circuit , 63...Second comparison circuit. Applicant NEC Corporation Agent
Patent attorney Umeo Yamauchi Figure 2

Claims (1)

[Claims] In a priority determination circuit that determines the priority among n-bit request signals from n units, accepts requests, and selects one unit, the requests of all n units are A first register with an n-bit width that holds information about which unit's request has been accepted up to the previous time within one cycle until the request is accepted, and a
A first logical AND circuit performs a logical AND with the request signal of the bit, and masks requests from units that have previously received a request within one cycle from among the current request; a second register with an n-bit width that holds mask information for accepting only requests lower than the requested request; a second AND circuit that performs a logical product and extracts only the requests that are lower than the previously accepted request; If it is shown that there is no lower request, the inputted request signal is selected; otherwise, the output of the second AND circuit is selected.
selector and the output of the first AND circuit indicate that there is no request from a unit that has not been previously accepted within one cycle in the input request signal. a second selector that selects the output of the selector and, if not, selects the output of the first AND circuit from among the plurality of requested bits among the n-bit outputs of the second selector; A decoder receives the output of the priority encoder that selects and outputs it, and decodes it into n bits, and the n-bit output from this decoder is ANDed with the contents of the first register, and If the currently accepted request is from a unit that has been previously accepted within one cycle, the first register operates to update or inhibit the first register. 3 AND circuit, and an exclusive OR that operates to perform an exclusive OR of the n-bit output of the third AND circuit and the contents of the first register, and update the first register. The n-bit output of this exclusive OR circuit is input, and when this input is “0”, it is assumed that one cycle has completed, and all bits are “1” and masked for the next n-bit request signal. When this input is not “0”,
a first comparison circuit that outputs the same as it is and sets it in the first register; a subtraction circuit that subtracts 1 from the n-bit output from the decoder to update the second register; When this input is "0", it is assumed that one cycle has completed and all bits are "1", so that there is no mask for the next n-bit request signal, and this input is "0". and a second comparator circuit that outputs it as is and sets it in the second register when the unaccepted request priority circuit is not received.