JPH01200460A - semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To omit the necessity for the time-division input/output of address and data and to realize input/output in the simple timing by performing the input/output of data through an input/output port terminal. CONSTITUTION:When a CNTL signal has an L level, the output of an AND gate 19 for inputs of both signals rd and ram serves as the output of a multiplexer 15 and is supplied to a control gate of a transmission gate 10. In the same way, the output of an AND gate 21 for inputs of both signals wr and arm serves as the output of a multiplexer 16 and is supplied to a control gate of a transmission gate 11. Thus, an address/data terminal 1 serves as an address-only terminal with a port input/output terminal 2 serving as a data input/output terminal respectively when the CNTL signal is set at an L level. In this case, the addresses and data are transferred via different terminals and therefore the complicated timing can be omitted for the time-division trans fer of addresses and data.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is a method in which the address and the data are multiplexed.
This invention relates to a semiconductor integrated circuit (hereinafter referred to as an IC) having input/output terminals.

[Prior art] Microcomputer systems have become increasingly complex and highly efficient, and under the influence of this, CPUs and memo systems have become increasingly complex. The number of pins for JIC and other peripheral work C is on the rise. On the other hand, in order to suppress the increase in pins, pins with dual functions are increasingly being used.

One such terminal is a multiplexed address terminal and data terminal. Below is a diagram showing conventional memory and input/output capo! The input/output circuit of the composite m-function memory C equipped with I-function will be explained. FIG. 3 is a block circuit diagram of the input/output circuit.

In the figure, RAM (7) is used as a memory for eight address trees and eight data trees, and is further equipped with an 8-bit input/output port. There is an address/data terminal (1) (A/DO to A/D7) in which an address terminal and a data terminal are multiplexed, and address input and data input/output are performed in a time-sharing manner.

The time-division timing is controlled by the signal from the address button enable terminal 5j (3) (ALE). A time-division timing chart of data input/output and data input/output is shown in FIG. The address input enters the address latch circuit (12), but the address latch circuit (12)
The ALE signal is input to the input control gate.

This address latch circuit (12) ALE signal is 1H
When the level changes from level to 1L#, the address belief at that time is taken in. The output of the address latch circuit (12) is not connected to the address bus (6), and the address bus (
6), the latched address signal is always output. No matter what level of signal is input from the address/data terminal (1) while the ALE signal is at 1L# level, the address latch output will not change.

Next, the ALE signal of 1 address 77 during the 1L# period.
RAMy' data is input or output from the '-data terminal (1). In the case of input and output, totsunumi gates (8) and (9) are used to prevent signal duplication.
) is provided. The signals controlling the transmission gates (8) and (9) are set to the 1H# level only at the timing of reading or writing, and these are AND gates.
) and (23) are output from 1. The output signals of (8) and (9) pass through the address/data terminal (1) and data path (5), respectively.
AM (7) Nζ is flowing.

On the other hand, in the port input/output signal Ji5 system, the port input/output terminal (2) (PORT~P
In order to separate the input signal and output signal from ORT7), these transmission gates) (tO) and (U) are used.
) to control the gate of A4D gate (18
) and (20) are connected to each other. AND
For the two-man power of gate (18), W r @ @ and Por
The t signal is input to the AND gate (20) by rdi
The I Porti signal is at 1H# level only when the port is used, the wr signal is at #H'' level only at the write timing, and the 1H# level is output only at the rd times signal successive timing. The signal system is such that port system data and RAM system data do not overlap on the data path (5).One of the input gates of AND gates (22) and (23) receives the output of the OR gate (17), but the data transmission gates (8) and (9) receive the output from the RAM
(7) Contains a logical OR of the ram and port signals to be used for both the port and the ram signal. Now, the third
In the case of the address/7'-event terminal (1) shown in Figures and Figure 4, since it also serves as a terminal, the bottle box is more convenient in terms of space saving than when using an isolated bottle. However, since time-sharing timing is used, in terms of time,
It was a loss. Moreover, especially with the recent trend towards higher speeds, AL
The timing of the E signal and address signal has become extremely fast, and the address bus has become more prone to malfunctions, so in that sense, multiple loss of addresses and data should be avoided as much as possible. It was a dual-purpose bottle that I didn't want to use.

[Problems to be Solved by the Invention] As described above, when using address/data terminals in which addresses and data are multiplexed in order to reduce the number of terminals in conventional memory cards, etc., address input timing and data input timing are It was necessary to provide output timing in a time-divided manner, which required very complicated timing.

This generator 8A was created to solve the above problems, and is equipped with an input/output port and an address and data port.
In construction C, which has a terminal with multiple data loss, when the input/output port is not used or during a period when it is not used, address or data signals are exchanged from the input/output port, and from the address/data terminal, The object of the present invention is to obtain an input/output circuit capable of exchanging signals of the other side or addresses.

[Means for Solving the Problems] Work C according to the present invention includes an input/output circuit for a terminal in which an address and f-number are multiplexed and an input/output circuit for an input/output port terminal, and It has a circuit that can input and output data from the address/data terminal using an input/output circuit for the output terminal.

In addition, a circuit is provided that can input an address from an address/data terminal using an input/output circuit for a port input/output terminal.

[Function J] From the use of the input/output circuit for port input/output terminals in this invention, when the port input/output terminals are not used,
Alternatively, during the period, either the address or gate signal from the address/data terminal may be sent from the port input/output terminal, and therefore only the other signal, data or address, may be exchanged from the address/data terminal.
It becomes unnecessary to perform complicated time-sharing timing from the address/data terminals.

[Embodiment J Hereinafter, one embodiment of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of the input/output circuit of process C of this invention.

In the figure (1) to (3), (5) to (12), (17
), (18), and (20) are the same as those explained in the conventional example of FIG. 3, so redundant explanations will be avoided. The new circuit according to this invention is a multiplexer (15) (16)
These are the controller μ signal terminal (4) (CN
Depending on the signal from TI,), it is determined whether the input/output ports transmission gates (10) and (11) work as the original input/output port FI & function or as the data input/output terminal of RAM (7). Sort out.

The operation will be explained below. When the CNTL signal is at 1L level, the rd multiplied signal and the RAM signal are ANDed by two people)
The output of (19) is input to the output of multiplexer (15) and the control frequency gate of (10). Similarly, the output of the two-man AND gate (21) of the wr multiplied signal RAM signal becomes the output of the multiplexer (16), and the transmission gate (
11) Enter the control gate.

Furthermore, IC and CNTL signals are simultaneously 3-person AND game) (
13) and (14), so the CNTL signal is #
When L#, these three-man power AND gates (13), (1
The outputs of 4) both go to the #L'' level /L/, and the transmission gates (8) and (9) remain closed, resulting in no data exchange from the address/data terminal (1). Therefore, the first
In the circuit system shown in the figure, CM'['L times signal'L#Rehe/L/
By setting VC, address/data terminal (1)
is an address-only terminal, and is a port input/output terminal (2).
becomes the gator input/output terminal. Therefore, in this case,
Since the address and gate are exchanged from different terminals, complicated timing for time-sharing the address and data is not required. In Fig. 1, when #H# level is applied to CN T LM@, the address/7-''-ta terminal (1) is a multiplex signal, and the port input/output terminal (2)
As a port! ! It becomes a circuit system with functions.

In addition, in the above embodiment, when the CNTl signal is "L#",
The address/data terminal (1) is shown as an address-only terminal, and the port input/output terminal (2) is shown as a data input/output terminal, but in other embodiments, the CNTL signal is set to "L".
In the case of K, the address/gator terminal (1) may be set exclusively for the gator terminal, and the port input/output terminal (2) may be set to be the at Vs input terminal. Figure 2 is a block circuit diagram of the input/output circuit in this case, where the multiplexer (24) connects the address/data terminal (1) and the port input/output terminal (2).
It is up to two people to select either one using the CNTL signal.

(22) (23) is an AND gate, (25) (26
) is a three-person AND gate.

Further, in the above embodiment, the RAM (7) is used as the memory, but the memory is not limited to the RAM (7) as long as it is a circuit element that exchanges data. Further, the number of bits of the address and port need not be limited to 8 bits, and any number of bits can be applied.

[Effect of the invention] As mentioned above, this F! According to 14, even if an address/data terminal is not used, or by using a period input/output port, the address/data terminal can be used as an address or data terminal, and in that case, The input/output ports can each be used as data or address terminals, and as a result, it is not necessary to input/output addresses and gaters in a time-sharing manner, and input/output can be performed with very simple timing.

Furthermore, since there is no need for time division, it is possible to increase the speed.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of the input/output circuit of construction C of the present invention, FIG. 2 is a block circuit diagram of the input/output circuit of construction C according to another embodiment of the invention, and FIG. 3 is a block circuit diagram of the input/output circuit of construction C of the present invention. A block circuit diagram of the input/output circuit of C, and FIG. 4 is a timing chart of a signal in which address and dark are multiplexed. In the figure, (1) is the address 77'-input terminal, (2) is the port input/output terminal, (3) is the address foot enable signal terminal, (4) is the control signal terminal, (5) is the data panel, and (6) is the address terminal. is the address bus, (7) is the RAM
, (8) to (11) al-lance mission gate,
(12)) i address latch circuit, (13), (14)
, (25) (26) is a three-person AND gate, (15)
, (16), (24) are multiplexers, (17) is O
R gates (18) to (23) are AND gates. In the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1” “”” tg-wA
Noke'-? 7: FAr' Fig. 2 n, n A No ri'-to Z4 Multiple hem length 25.2t + 3 Ino AtvD gate Fig. 3 Fig. 4 LE Procedural amendment (voluntary) 1. Indication of the case: Japanese Patent Application No. 63-260182, Title of the invention: Semiconductor integrated circuit 3, Representative of the person making the amendment: Moriya Shiki, 4, Agent: 5, Drawing to be amended 6, Contents of the amendment: Complete drawing (Figure 2) Correct as shown in the attached sheet. 7. Attached document catalog drawing (Figure 2) 1 or more copies

Claims (1)

[Claims] An integrated circuit having terminals through which addresses and data are multiplexed and input/output, and also equipped with input/output port terminals, characterized by having an input/output circuit capable of inputting/outputting the data from the input/output port terminals. semiconductor integrated circuits.