JPH01200514A - Insulation covered gold or gold alloy extra fine wire for bonding semiconductor element - Google Patents

Insulation covered gold or gold alloy extra fine wire for bonding semiconductor element

Info

Publication number
JPH01200514A
JPH01200514A JP63024630A JP2463088A JPH01200514A JP H01200514 A JPH01200514 A JP H01200514A JP 63024630 A JP63024630 A JP 63024630A JP 2463088 A JP2463088 A JP 2463088A JP H01200514 A JPH01200514 A JP H01200514A
Authority
JP
Japan
Prior art keywords
gold
wire
thickness
layer
gold alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63024630A
Other languages
Japanese (ja)
Other versions
JP2737137B2 (en
Inventor
Tamotsu Mori
保 森
Toshinori Ishii
利昇 石井
Masayuki Tanaka
正幸 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Metal Corp
Original Assignee
Mitsubishi Metal Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Metal Corp filed Critical Mitsubishi Metal Corp
Priority to JP63024630A priority Critical patent/JP2737137B2/en
Publication of JPH01200514A publication Critical patent/JPH01200514A/en
Application granted granted Critical
Publication of JP2737137B2 publication Critical patent/JP2737137B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/521—Structures or relative sizes of bond wires
    • H10W72/522—Multilayered bond wires, e.g. having a coating concentric around a core
    • H10W72/523—Multilayered bond wires, e.g. having a coating concentric around a core characterised by the structures of the outermost layers, e.g. multilayered coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/555—Materials of bond wires of outermost layers of multilayered bond wires, e.g. material of a coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Insulated Conductors (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce an occurrence of a trouble due to electrical short-circuit and the like by forming an insulation cover layer of a specific thickness on the surface of a gold or a gold alloy extra fine wire and a lubrication layer of a specific thickness on the aforesaid insulation cover layer. CONSTITUTION:An insulation covered or alloy extra fine wire 3 is bonded to a silicon chip 8 on a lead frame 7 via the formation of a ball bonding part 9 and then the wire is paid out while a capillary 4 is being moved toward an electrode 5. Furthermore, the wire is extruded to the electrode 5 with the capillary 4, thereby forming a wedge bond part 6 for wire con nection to the electrode 5. In this case, the thickness of an insulation cover layer 2 is 0.5 to 1.5Xm and the thickness of an lubrication layer 1 is 0.05 to 1.0mum, thereby keeping breakdown voltage at the predetermined voltage and eliminating a trouble for wire connection due to the small exposure of a new surface area at the junction interface of a wedge point.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、集積回路（ＩＣ，ＬＳＩ、　　トランジス
ター等）素子上の電極と、回路配線基板上（リードフレ
ーム、セラミック基板等）の導体配線との間を接続する
絶縁被膜ボンディング用金または金合金極細線に関する
ものである。[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to electrodes on integrated circuit (IC, LSI, transistor, etc.) elements and conductor wiring on circuit wiring boards (lead frames, ceramic substrates, etc.). The present invention relates to a gold or gold alloy ultrafine wire for bonding an insulating coating between the two.

〔従来の技術〕[Conventional technology]

従来、この種のボンディング用金または金合金線は、直
径＝１８〜５０μｓ程度の裸の金または金合金極細線が
使用されていた。しかしながら従来のボンディング用金
または金合金極細線では、多ピン高密度配線の場合に、
ワイヤの少しの曲りでも隣のワイヤと接触し短絡が発生
していた。Conventionally, as this type of bonding gold or gold alloy wire, a bare gold or gold alloy ultrafine wire with a diameter of about 18 to 50 μs has been used. However, with conventional gold or gold alloy ultrafine wires for bonding, in the case of high-density wiring with many pins,
Even a slight bend in a wire would cause it to come into contact with an adjacent wire, causing a short circuit.

またワイヤボンド後は、接触がなく正常であっても、レ
ジンモールド（樹脂封止）時のワイヤの流れにより短絡
が発生するという聞届があった。Furthermore, there have been reports that even if there is no contact after wire bonding and there is no contact, short circuits may occur due to the flow of the wire during resin molding (resin sealing).

これらの問題解決のために樹脂材の一層構造による絶縁
被覆ワイヤも考案されている。To solve these problems, an insulated wire having a single layer structure made of resin has been devised.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、上記公知の絶縁被覆ワイヤは、ボンディング
装置のクランパーおよびキャピラリー通過時の摩擦係数
が大きいため、安定した繰り出しが出来ず、そのために
ループ形状の安定したワイヤボンディングが不可能であ
った。However, the above-mentioned known insulated wire has a large coefficient of friction when passing through the clamper and capillary of the bonding device, and therefore cannot be stably fed out, making it impossible to perform wire bonding with a stable loop shape.

特に金または金合金極細線の絶縁被覆ワイヤは、金また
は金合金自体が軟かく強度が低いために、クランパーお
よびキャピラリー通過時の摩擦係数が大きいとスムーズ
な繰り出しができず、そのため適正なループが形成され
ず、断線することも毎々あった。In particular, insulated gold or gold alloy ultra-fine wires cannot be smoothly fed out due to the high friction coefficient when passing through the clamper and capillary because the gold or gold alloy itself is soft and has low strength. There were cases where the wires were not formed and the wires were broken.

〔課題を解決するための手段〕[Means to solve the problem]

そこで、本発明者等は、上記ボンディング装置のクラン
パーおよびキャピラリー通過時の摩擦係数の小さい絶縁
被覆層を有する金または金合金極細線を開発すべく研究
を行なった結果、絶縁被覆層を有する金または金合金極
細線の表面に更に潤滑層を被覆すればよいという知見を
得たのである。Therefore, the present inventors conducted research to develop a gold or gold alloy ultrafine wire having an insulating coating layer that has a small coefficient of friction when passing through the clamper and capillary of the above-mentioned bonding device. They discovered that it is sufficient to coat the surface of the ultrafine gold alloy wire with a lubricating layer.

この発明は、かかる知見にもとづいてなされたものであ
って、 絶縁被覆層を有する金または金合金極細線の表面に潤滑
層を形成してなる半導体素子ボンディング用絶縁被覆金
または金合金極細線に特徴を有するものである。The present invention was made based on this knowledge, and provides an insulating coated gold or gold alloy ultrafine wire for semiconductor element bonding, which is formed by forming a lubricating layer on the surface of the gold or gold alloy ultrafine wire having an insulating coating layer. It has characteristics.

第１図は、この発明の半導体素子ボンディング用絶縁被
覆金または金合金極細線の断面概略図、第２図は、上記
絶縁被覆層または金合金極細線を用いてワイヤボンディ
ングしている状態を示す概略図である。FIG. 1 is a schematic cross-sectional view of an insulating coated gold or gold alloy ultrafine wire for semiconductor element bonding according to the present invention, and FIG. 2 shows a state in which wire bonding is performed using the above insulating coating layer or gold alloy ultrafine wire. It is a schematic diagram.

上記第１図を用いて、この発明の半導体素子ボンディン
グ用絶縁被覆金または金合金極細線について説明すると
、１は潤滑層、２は絶縁被覆層、３は金または金合金極
細線である。上記絶縁被覆層２はポリウレタン、ポリエ
チレンまたはエポキシからなり、その層厚は０，５〜１
．５　ｍｕが好ましい。The insulating coated gold or gold alloy ultrafine wire for semiconductor element bonding of the present invention will be described with reference to FIG. 1. 1 is a lubricating layer, 2 is an insulating coating layer, and 3 is a gold or gold alloy ultrafine wire. The insulation coating layer 2 is made of polyurethane, polyethylene or epoxy, and has a thickness of 0.5 to 1
．． 5 mu is preferred.

上記潤滑層１はテフロンまたは界面活性剤′（具体的に
は、アニオン界面活性剤または非イオン活性剤、例えば
、ポリオキシエチレンアルキルエーテルサルフェートま
たはポリオキシエチレンアルキルエーテル等）からなり
、その層厚は０．０５〜１．０μｓが好ましい。The lubricating layer 1 is made of Teflon or a surfactant' (specifically, an anionic surfactant or a nonionic surfactant, such as polyoxyethylene alkyl ether sulfate or polyoxyethylene alkyl ether), and the layer thickness is 0.05 to 1.0 μs is preferable.

上記第１図に示されたこの発明の絶縁被覆層または金合
金極細線を用いて半導体素子にワイヤボンディングする
状態が第２図に示されている。FIG. 2 shows a state in which the insulating coating layer or gold alloy ultrafine wire of the present invention shown in FIG. 1 is wire-bonded to a semiconductor element.

まず絶縁被覆層または金合金極細線をリードフレーム７
上のＳｉチップ８上にボールボンド部９を形成して接合
し、ついでキャピラリー４をリード電極５の方向に移動
しつつワイヤを繰り出し、上記ワイヤをキャピラリー４
によりリード電極５に押圧してウェッジボンド部６を形
成し、リード電極５に接合する。First, an insulating coating layer or gold alloy ultrafine wire is attached to the lead frame 7.
A ball bond part 9 is formed on the upper Si chip 8 for bonding, and then the wire is fed out while moving the capillary 4 in the direction of the lead electrode 5, and the wire is attached to the capillary 4.
is pressed against the lead electrode 5 to form a wedge bond portion 6 and bonded to the lead electrode 5.

絶縁被覆層２の厚みを０，５〜１．５　ｔｌｒａとした
理由は、その層厚が０．５μｓ未満では絶縁破壊電圧を
５０Ｖ以上の一定値以上に確保することができず、−方
リード電極５側のウェッジボンド部６を形成する時は層
厚が１．５ＺＺＩ１１を越えると接合界面での新生面の
露出が少く、拡散が抑制され充分な接合強度が得られな
くなる。よって、絶縁被覆層２の層厚は０．５〜１．５
−に定めた。The reason why the thickness of the insulating coating layer 2 is set to 0.5 to 1.5 tlra is that if the layer thickness is less than 0.5 μs, the dielectric breakdown voltage cannot be secured to a certain value of 50 V or more. When forming the wedge bond part 6 on the electrode 5 side, if the layer thickness exceeds 1.5ZZI11, the exposure of the new surface at the bonding interface will be small, diffusion will be suppressed, and sufficient bonding strength will not be obtained. Therefore, the layer thickness of the insulation coating layer 2 is 0.5 to 1.5
−.

また、潤滑層の厚みを０．０５〜１．Ｏｕｒｎとした理
由は、その層厚が０．０５ｔｌｎ未満では潤滑層として
の充分な効果が得られず、一方、■、０−を越えると上
記絶縁被覆層と同様に、ウェッジボンド部６の成形時に
接合界面での新生面の露出が少く、拡散が抑制され充分
な接合強度が得られなくなるために１、Ｏｔｍ以下とし
た。Further, the thickness of the lubricating layer is set to 0.05 to 1. The reason for choosing Own is that if the layer thickness is less than 0.05 tln, sufficient effect as a lubricating layer cannot be obtained; In some cases, the exposure of the new surface at the bonding interface is small, diffusion is suppressed, and sufficient bonding strength cannot be obtained, so the thickness was set to 1,000 tm or less.

ボールボンド部９の成形時には、電気トーチの放電エネ
ルギーにより被覆剤は溶けてしまうために、絶縁被覆層
および潤滑層の厚さに関係なく良好なボールボンド部９
が形成できるが、上記絶縁被覆層２および潤滑層３が厚
いとウェッジボンド部６の接合に支障をきたすのである
。When forming the ball bond part 9, the coating material is melted by the discharge energy of the electric torch, so the ball bond part 9 can be formed in good condition regardless of the thickness of the insulating coating layer and the lubricating layer.
However, if the insulating coating layer 2 and the lubricating layer 3 are thick, it will hinder the bonding of the wedge bond portion 6.

〔実　施　例〕〔Example〕

つぎに、この発明を実施例にもとづいて具体的に説明す
る。Next, the present invention will be specifically explained based on examples.

実施例　１ 直径＝２５ｔ１ｍの全極細線に層厚：０．５μｓのポリ
エチレン絶縁被覆層を被覆し、その上にテフロンからな
る層厚：　０．０５ａｍの潤滑層を形成して半導体素子
ボンディング用絶縁被覆金極細線を作製した。Example 1 All ultra-fine wires with a diameter of 25t1m were coated with a polyethylene insulation coating layer with a layer thickness of 0.5μs, and a lubricant layer of Teflon with a thickness of 0.05am was formed thereon to provide insulation for semiconductor element bonding. A coated gold ultrafine wire was fabricated.

この絶縁被覆層極細線を用いて半導体装置の実装を行な
い、故意にワイヤの短絡やショートを発生させたが、電
気的ショートとはならず、レジンモールド後の不良の発
生も皆無であった。A semiconductor device was mounted using this insulating coating layer ultrafine wire, and although short circuits and shorts were intentionally caused in the wires, no electrical shorts occurred, and no defects occurred after resin molding.

実施例　２ 直径二３３頗の全極細線に層厚：１．５庫のポリウレタ
ン絶縁被覆層を被覆し、その上に界面活性剤のポリオキ
シエチレンアルキルエーテルを層厚：１．０μｓとなる
ように被覆して半導体素子ボンディング用絶縁被覆金極
細線を作製した。Example 2 All ultra-fine wires with a diameter of 233 mm were coated with a polyurethane insulation coating layer with a layer thickness of 1.5 mm, and a surfactant polyoxyethylene alkyl ether was applied on top of the polyurethane insulation coating layer to a layer thickness of 1.0 μs. An insulating coated ultrafine gold wire for bonding semiconductor devices was prepared by coating the gold wire with

この絶縁被覆層極細線を用いて半導体装置の実装を行な
い、故意にワイヤの短絡やショートを発生させたが、電
気的ショートとはならず、レジンモールド後の不良の発
生も皆無であった。A semiconductor device was mounted using this insulating coating layer ultrafine wire, and although short circuits and shorts were intentionally caused in the wires, no electrical shorts occurred, and no defects occurred after resin molding.

〔発明の効果〕〔Effect of the invention〕

この発明の絶縁被覆層または金合金極細線は、特に多ピ
ン高密度半導体素子のワイヤボンディングに効果が大き
く、電気的ショート等による不良の発生も皆無であるか
ら実装歩留りに著しい向上をもたらす。The insulating coating layer or the gold alloy ultrafine wire of the present invention is particularly effective in wire bonding of multi-pin high-density semiconductor devices, and there is no occurrence of defects due to electrical shorts, resulting in a significant improvement in the mounting yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、この発明の半導体素子ボンディング用絶縁被
覆金または金合金極細線の断面概略図、第２図は、ワイ
ヤボンディングの状態を示す概略図。 １・・・潤滑層　　　　　　　２・・・絶縁被覆層３・
・・金または金合金極細線FIG. 1 is a schematic cross-sectional view of an insulating coated gold or gold alloy ultrafine wire for semiconductor element bonding according to the present invention, and FIG. 2 is a schematic view showing the state of wire bonding. 1... Lubricating layer 2... Insulating coating layer 3...
・・Gold or gold alloy ultrafine wire

Claims (1)

【特許請求の範囲】 １、金または金合金極細線の表面に絶縁被覆層を形成し
、上記絶縁被覆層の上に潤滑層を形成してなることを特
徴とする半導体素子ボンディング用絶縁被覆金または金
合金極細線。 ２、上記絶縁被覆層は、層厚：０．５〜１．５μｍであ
り、潤滑層は、層厚：０．０５〜１．０μｍであること
を特徴とする請求項１記載の半導体素子ボンディング用
絶縁被覆金または金合金極細線。 ３、上記絶縁被覆層は、ポリウレタン、ポリエチレンま
たはエポキシからなり、上記潤滑層は、テフロンまたは
界面活性剤からなることを特徴とする請求項１または２
記載の半導体素子ボンディング用絶縁被覆金または金合
金極細線。[Claims] 1. An insulating coated gold for semiconductor element bonding, characterized in that an insulating coating layer is formed on the surface of a gold or gold alloy ultrafine wire, and a lubricating layer is formed on the insulating coating layer. Or gold alloy ultra-fine wire. 2. The semiconductor element bonding according to claim 1, wherein the insulating coating layer has a thickness of 0.5 to 1.5 μm, and the lubricating layer has a thickness of 0.05 to 1.0 μm. Insulating coated gold or gold alloy ultrafine wire. 3. Claim 1 or 2, wherein the insulating coating layer is made of polyurethane, polyethylene or epoxy, and the lubricating layer is made of Teflon or a surfactant.
The insulating coated gold or gold alloy ultrafine wire for semiconductor element bonding described above.
JP63024630A 1988-02-04 1988-02-04 Insulated gold or gold alloy extra fine wire for semiconductor element bonding Expired - Lifetime JP2737137B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01167040U (en) * 1988-05-16 1989-11-22
JPH03165044A (en) * 1989-11-22 1991-07-17 Tanaka Denshi Kogyo Kk Covered wire

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583239A (en) * 1981-06-29 1983-01-10 Seiko Epson Corp Bonding wire
JPS59167044A (en) * 1983-03-11 1984-09-20 Mitsubishi Metal Corp Gold or gold alloy fine wire for wire-bonding semiconductor device
JPS62291808A (en) * 1986-06-11 1987-12-18 古河電気工業株式会社 Insulated wire with improved working resistance

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583239A (en) * 1981-06-29 1983-01-10 Seiko Epson Corp Bonding wire
JPS59167044A (en) * 1983-03-11 1984-09-20 Mitsubishi Metal Corp Gold or gold alloy fine wire for wire-bonding semiconductor device
JPS62291808A (en) * 1986-06-11 1987-12-18 古河電気工業株式会社 Insulated wire with improved working resistance

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01167040U (en) * 1988-05-16 1989-11-22
JPH03165044A (en) * 1989-11-22 1991-07-17 Tanaka Denshi Kogyo Kk Covered wire

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