JPH01200531A - Malfunction prevention device for signal transmission circuits including double winding latching relays - Google Patents

Malfunction prevention device for signal transmission circuits including double winding latching relays

Info

Publication number
JPH01200531A
JPH01200531A JP63024337A JP2433788A JPH01200531A JP H01200531 A JPH01200531 A JP H01200531A JP 63024337 A JP63024337 A JP 63024337A JP 2433788 A JP2433788 A JP 2433788A JP H01200531 A JPH01200531 A JP H01200531A
Authority
JP
Japan
Prior art keywords
diode
coil
circuit
induced electromotive
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63024337A
Other languages
Japanese (ja)
Other versions
JPH0580775B2 (en
Inventor
Tadashi Adachi
正 足立
Yoshiaki Hashiya
嘉朗 橋谷
Yoshiaki Onishi
良明 大西
Kazuo Sakitani
崎谷 和男
Satoshi Inoue
聡 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63024337A priority Critical patent/JPH01200531A/en
Publication of JPH01200531A publication Critical patent/JPH01200531A/en
Publication of JPH0580775B2 publication Critical patent/JPH0580775B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To prevent the malfunction of a signal transmission circuit including a latch relay by connecting the coil of the compound wound latch relay to the first diode in parallel and connecting the series circuit of a reverse polarity second diode and the latch relay coil lo a capacitor in parallel. CONSTITUTION:When a set pulse Va is given to a set coil 2a, induced electromotive voltage generated respectively at leading and trailing ports of the pulse in a reset coil 2b is shunted by the first diode Db. The second diode D2 is also involved in the aforesaid process. Also, the other side of the induced electromotive voltage (this has reverse polarity and the upper side of the reset coil 2b is positive and the lower side thereof is negative) has reverse polarity against the second diode D2' and therefore this diode D2, comes to have high impedance. As a result, shunt effect due to a capacitor C2 connected in parallel to the series circuit of the second diode D2 and the reset coil 2b works very effectively and the induced electromotive voltage is well suppressed. According to the aforesaid construction, a signal free from induced electromotive voltage is inputted to a post-stage circuit 3 as shown in Vb and the circuit 3 is free from malfunction.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、前段回路に複巻線ラッチリレーとともに後段
回路を接続して前段回路から後段回路に論理信号を伝送
せざるを得ない場合に有用である複巻線ラッチリレーを
含む信号伝送回路の誤動作防止装置に関する。
[Detailed Description of the Invention] Industrial Field of Application The present invention is useful when a rear stage circuit is connected to a front stage circuit together with a multi-winding latch relay to transmit a logic signal from the front stage circuit to the rear stage circuit. The present invention relates to a malfunction prevention device for a signal transmission circuit including a certain multi-winding latch relay.

従来の技術 本発明の前提となる回路装置は第7図に示される。この
回路は、前段回路1に複巻線ラッチリレー2を接続する
とともに後段回路3を接続する構成を備え、複巻線ラッ
チリレー2のセットコイル2aとリセットコイル2bに
はダイオードD&+Dbを各々並列接続しであるもので
ある。これらのダイオードD、  ・Dbはリレーコイ
ルに発生する逆起電圧防止用として慣用されているもの
であり、セットコイル2&、リセットコイル2bの駆動
電流を停止した時にそれらのコイルに発生する逆起電圧
をシャントして、逆起電圧が直流電源TRYを介して前
段回路1内のトランジスJQa 、Qbに印加されない
ようにし、トランジスタQΔ、Qbの過電圧破壊を防止
するものである。例えば、トランジスタQaをセントパ
ルスでオンしてセントコイル2aに駆動電流を流す場合
のトランジスタQaとセットコイル2&との接続点の電
圧vaは、第8図実線に示す通りであり、点線にて示さ
れる逆起電圧はダイオードD、にてシャントされて存在
しない。従って、トランジスタQaには逆起電圧が印加
されなく保護される。
BACKGROUND OF THE INVENTION A circuit device on which the present invention is based is shown in FIG. This circuit has a configuration in which a multi-winding latch relay 2 is connected to a front-stage circuit 1 and a second-stage circuit 3 is connected, and diodes D&+Db are connected in parallel to a set coil 2a and a reset coil 2b of the multi-winding latch relay 2, respectively. It is something that is true. These diodes D and Db are commonly used to prevent back electromotive force generated in the relay coil, and prevent back electromotive force generated in those coils when the drive current of set coil 2 & reset coil 2b is stopped. This shunts the back electromotive force from being applied to the transistors JQa and Qb in the front stage circuit 1 via the DC power supply TRY, thereby preventing overvoltage damage to the transistors QΔ and Qb. For example, when the transistor Qa is turned on by a cent pulse to cause a drive current to flow through the cent coil 2a, the voltage va at the connection point between the transistor Qa and the set coil 2& is as shown by the solid line in FIG. 8, and is shown by the dotted line. The back electromotive voltage generated is shunted by the diode D and does not exist. Therefore, the transistor Qa is protected from being applied with a back electromotive voltage.

発明が解決しようとする課題 ところが、複巻線ラッチリレー2を用いる場合には別の
解決すべき課題が存在する。すなわち、複巻線ラッチリ
レー2はセットコイル21Lとリセットコイル2bとを
磁気的に結合してあり、各コイルに交互にパルス電流を
流すことによって図示しないリレー接点をフリップフロ
ップ的に動作させる作用を備え、このリレー接点により
図示しない負荷を選択的に制御するものである。この場
合、第8図実線のようにセットコイル2&をv2Lに示
すセットパルスにて駆動した時に、リセットコイル2b
にはセットパルスの立下りと立上り部分で互いに逆極性
の誘導起電圧が発生する。この誘導起電圧のうち一方は
ダイオードDb にてシャントされるが、他方は第8図
vb(トランジスタQbとリセットコイル2bとの接続
点電圧)の実線に示すように直流電源vnrを介して現
われ、後段回路2の論理に誤動作を与えてしまう。この
場合、後段回路2の入力を前段回路1内のトランジスタ
Qa  、Qbのベース側からインバータを介して取れ
ば何ら問題にはならないが、前段回路1が集積回路化さ
れておりそのような信号取出し端子がないような場合は
解決しなければならない課題としてクローズアップされ
る。
Problems to be Solved by the Invention However, when using the multi-winding latch relay 2, there is another problem to be solved. That is, the double-winding latch relay 2 has a set coil 21L and a reset coil 2b magnetically coupled, and has the effect of operating relay contacts (not shown) like a flip-flop by alternately passing a pulse current through each coil. This relay contact selectively controls a load (not shown). In this case, when the set coil 2& is driven with the set pulse shown by v2L as shown by the solid line in FIG. 8, the reset coil 2b
Induced electromotive voltages of opposite polarity are generated at the falling and rising portions of the set pulse. One of these induced electromotive voltages is shunted by the diode Db, but the other appears via the DC power supply vnr as shown by the solid line in FIG. 8 vb (voltage at the connection point between the transistor Qb and the reset coil 2b) This will cause the logic of the subsequent circuit 2 to malfunction. In this case, there will be no problem if the input to the rear circuit 2 is taken from the base side of the transistors Qa and Qb in the front circuit 1 via an inverter, but since the front circuit 1 is an integrated circuit, such signal extraction is not possible. Cases where there are no terminals are highlighted as issues that must be solved.

本発明は、このような背景にもとづいて発明されたもの
であり、複巻線ラッチリレーを含む信号伝送回路の誤動
作を適確に防止する目的を有する。
The present invention was invented based on this background, and has an object to appropriately prevent malfunctions of a signal transmission circuit including a multi-winding latch relay.

課題を解決するだめの手段 本発明は、前段回路に複巻線ラッチリレーとともに後段
回路を接続する構成を備え、前記複巻線ラッチリレーの
セントコイルとリセットコイルには第1ダイオードを各
々並列接続し、前記コイルのうちの少なくとも前記後段
回路に接続される方のコイルには、前記第1ダイオード
とは逆向きの第2ダイオードを直列接続するとともにこ
のコイルと前記第2ダイオードの直列回路にコンデンサ
を並列接続したことを特徴とする複巻線ラッチリレーを
含む信号伝送回路の誤動作防止装置を構成する。
Means for Solving the Problems The present invention is provided with a structure in which a post-stage circuit is connected to a pre-stage circuit together with a multi-winding latch relay, and a first diode is connected in parallel to a cent coil and a reset coil of the multi-winding latch relay, respectively. A second diode having a direction opposite to the first diode is connected in series to at least one of the coils that is connected to the subsequent circuit, and a capacitor is connected to the series circuit of this coil and the second diode. The present invention constitutes a malfunction prevention device for a signal transmission circuit including a multi-winding latch relay, which is characterized in that the following are connected in parallel.

作用 本発明によれば、複巻線ラッチリレーのコイルに発生し
た他方のコイルからの誘導起電圧を適確にシャントでき
後段回路を誤動作させない。すなわち、誘導起電圧の一
方は第1ダイオードにてシャントされ、他方はこの誘導
起電圧に対し逆極性である第2ダイオードの高インピー
ダンス成分を含む第2ダイオードと複巻線ラッチリレー
のコイルとの直列回路をコンデンサでシャントスるコト
により抑圧される。そして、コンデンサは高インピーダ
ンス成分をシャントするので、低容量のもので充分であ
り、低価格化ならびに省スペース化に寄与し、リレー接
点の応答も鈍くならない。
According to the present invention, it is possible to appropriately shunt the induced electromotive force generated in the coil of the multi-winding latch relay from the other coil, thereby preventing malfunction of the subsequent stage circuit. That is, one side of the induced electromotive force is shunted by the first diode, and the other side is shunted by the second diode, which includes a high impedance component of the second diode, which has the opposite polarity to this induced electromotive force, and the coil of the multi-winding latch relay. It is suppressed by shunting the series circuit with a capacitor. Since the capacitor shunts high impedance components, a low capacitance capacitor is sufficient, contributing to cost reduction and space saving, and the response of the relay contact does not become dull.

実施例 次に本発明の実施例を第1図〜第6図を参照して説明す
る。
Embodiment Next, an embodiment of the present invention will be described with reference to FIGS. 1 to 6.

実施例1(第1図、第2図参照) この実施例1による回路は、第7図に示した本発明の前
提回路と次の点において異なる。すなわち、複巻線ラッ
チリレー2のセットコイル2aとリセットコイル2bに
は、ダイオード%+Dl)(本発明では後述する別のダ
イオードと区別するため、以下第1ダイオードと称す)
とは逆向きの第2ダイオードD1.D2 を各々直列接
続するとともに、セットコイル2aと第2ダイオードD
Embodiment 1 (See FIGS. 1 and 2) The circuit according to this embodiment 1 differs from the prerequisite circuit of the present invention shown in FIG. 7 in the following points. That is, the set coil 2a and reset coil 2b of the double winding latch relay 2 include a diode (%+Dl) (hereinafter referred to as a first diode in order to distinguish it from another diode described later in the present invention).
The second diode D1. D2 are connected in series, and the set coil 2a and the second diode D
.

との直列回路ならびにリセットコイル2bと第2ダイオ
ードD2との直列回路にはコンデンサC4゜C2を各々
並列接続したことにある。なお、第1ダイオードDa、
Dbは各々、第2ダイオードD、 ID2  を介して
セットコイル22L、リセットコイル2bに並列接続さ
れる。
Capacitors C4 and C2 are connected in parallel to the series circuit between the reset coil 2b and the second diode D2, respectively. Note that the first diode Da,
Db is connected in parallel to the set coil 22L and reset coil 2b via second diodes D and ID2, respectively.

このような構成において、第2図Va のようにセット
コイル2aにセットパルスを与えた時、このセットパル
スの立下りと立上りの部分でリセットコイル2bにそれ
ぞれ発生する誘導起電圧は次のような回路動作によって
抑圧される。すなわち、誘導起電圧の一方は本発明の前
提回路第7図による場合と同様に第1ダイオードDb 
によってシャントされる。なお、この実施例におけるシ
ャント作用は、第2ダイオードD2  も介して行なわ
れる。
In such a configuration, when a set pulse is applied to the set coil 2a as shown in Fig. 2 Va, the induced electromotive force generated in the reset coil 2b at the falling and rising parts of this set pulse is as follows. Suppressed by circuit operation. That is, one of the induced electromotive voltages is caused by the first diode Db as in the case of the prerequisite circuit of the present invention shown in FIG.
shunted by. Note that the shunt effect in this embodiment is also performed via the second diode D2.

又、誘導起電圧の他方(前記のものとは逆極性であり、
第1図においてリセットコイル2bの上側が士、下側か
−となる)は、第2ダイオードD2−に対して逆極性の
ためにこの第2ダイオードD2は高インピーダンスとな
り、第2ダイオードD2とリセットコイル2bとの直列
回路(高インピーダンス)に並列接続されるコンデンサ
C2によるシャント作用が極めて有効に作用し、コンデ
ンサC2が相当低容量の場合でもコンデンサC2のイン
ピーダンスが相対的に相当小さいものであることから、
充分に抑圧される。ちなみに、第2ダイオードD2  
の両端をショートしてリセットコイル2bに第1ダイオ
ードDb とコンデンサC2とが単に並列接続される場
合には、コンデンサC2の容量として数μFのものが必
要になるとともに、図示しないリレー接点の応答が相当
鈍くなるが、本発明では、コンデンサC2は0.01μ
F程度で誘導起電圧を充分に抑圧できるとともに、リレ
ー接点の応答にも側段支障をきたすことはない。このよ
うにして第2図vbに示すように後段回路3には誘導起
電圧のない信号が入力されるため、後段回路3が誤動作
することがない。なお、もちろんリセットコイル2bに
リセットパルスが供給される場合でもセントコイル2’
a側の第1ダイオードDa 、第2ダイオードD1.コ
ンデンサC1が作用して後段回路3に誤動作を与えない
Also, the other side of the induced electromotive force (opposite polarity to the above one,
In FIG. 1, the upper side of the reset coil 2b is opposite to the second diode D2-, so the second diode D2 has a high impedance, and the reset coil 2b and the second diode D2 have opposite polarity. The shunt effect of capacitor C2 connected in parallel to the series circuit (high impedance) with coil 2b is extremely effective, and even if capacitor C2 has a fairly low capacity, the impedance of capacitor C2 is relatively small. from,
sufficiently suppressed. By the way, the second diode D2
If the first diode Db and capacitor C2 are simply connected in parallel to the reset coil 2b by shorting both ends of the capacitor C2, a capacitance of several μF is required for the capacitor C2, and the response of the relay contact (not shown) is In the present invention, the capacitor C2 is 0.01μ, although it becomes considerably dull.
The induced electromotive voltage can be sufficiently suppressed at around F, and the response of the relay contact will not be affected by the side stage. In this way, as shown in FIG. 2vb, a signal with no induced electromotive force is input to the subsequent stage circuit 3, so that the subsequent stage circuit 3 does not malfunction. Of course, even when the reset pulse is supplied to the reset coil 2b, the center coil 2'
The first diode Da on the a side, the second diode D1 . Capacitor C1 acts to prevent malfunction from occurring in the subsequent stage circuit 3.

実施例2(第3図〜第6図参照) この実施例では、複巻線ラッテリレー2のセットコイル
2+L、リセットコイル2bのうちの後段回路3に接続
される方のコイル、すなわちリセットコイル2bには、
実施例1と同様に第1ダイオードDb 、第2ダイオー
ドD2+コンデンサC2を接続し、後段回路3に接続さ
れていない方のコイル、すなわちセットコイル2乙には
実施例1の第2ダイオードD1.コンデンサC1が接続
されず、第1ダイオードD&が接続されている。
Embodiment 2 (See FIGS. 3 to 6) In this embodiment, the set coil 2+L and reset coil 2b of the multi-winding latte relay 2 are connected to the subsequent circuit 3, that is, the reset coil 2b. for,
As in the first embodiment, the first diode Db, the second diode D2 and the capacitor C2 are connected, and the second diode D1. Capacitor C1 is not connected, and first diode D& is connected.

このような構成では、第4図Vaのようにセットコイル
2&にセットパルスを与えた時のvb加電圧、実施例1
と同じく誘導起電圧が抑圧されているため、後段回路3
を誤動作させない。又、第6図vb のようにリセット
コイル2bにリセットパルスを与えた時のVa定電圧は
誘導起電圧が現われるが、セットコイル2a側は後段回
路3に接続されていないため、この誘導起電圧は後段回
路3の動作に何ら問題がない。
In such a configuration, as shown in FIG.
Similarly, the induced electromotive force is suppressed, so the subsequent circuit 3
Do not allow it to malfunction. Also, as shown in FIG. 6vb, when a reset pulse is given to the reset coil 2b, an induced electromotive force appears in the Va constant voltage, but since the set coil 2a side is not connected to the subsequent circuit 3, this induced electromotive force There is no problem in the operation of the subsequent stage circuit 3.

このように、この実施例から明らかな通り、複巻線ラッ
チリレー2の各コイルには第1ダイオードを各々並列接
続すべきであるが、前記コイルのうちの少なくとも後段
回路3に接続される方のコイルに、第1ダイオードとは
逆向きの第2ダイオードを直列接続するとともにこのコ
イルと第2ダイオードの直列回路にコンデンサを並列接
続すれば、本発明の目的が達成される。
As is clear from this embodiment, a first diode should be connected in parallel to each coil of the double-winding latch relay 2, but at least one of the coils connected to the subsequent circuit 3 should be connected in parallel to each coil. The object of the present invention can be achieved by connecting a second diode in series with the coil in a direction opposite to that of the first diode, and connecting a capacitor in parallel to the series circuit of this coil and the second diode.

実施例3(第6図参照) この実施例では、第1ダイオードDb  を第2ダイオ
ードD2  を介さずにリセットコイル2bに並列接続
した構成であり、前記両実施例で説明した誘導起電圧の
抑圧作用と何ら変わりはない。丑だ、もちろん、実施例
1の第1ダイオードDiL、Di)や実施例2の第1ダ
イオードDb を本実施例のように接続替えすることが
できる。
Embodiment 3 (See Fig. 6) In this embodiment, the first diode Db is connected in parallel to the reset coil 2b without intervening the second diode D2, and the induced electromotive voltage can be suppressed as described in both embodiments. There is no difference in the action. Of course, the connections of the first diodes DiL, Di) of the first embodiment and the first diode Db of the second embodiment can be changed as in the present embodiment.

発明の効果 本発明によれば、前段回路に複巻線ラッチリレーととも
に後段回路を接続して前段回路から後段回路に論理信号
を伝送する場合に、前記リレーのコイルに発生する誘導
起電圧を適確に抑圧できるため、後段回路を誤動作させ
ない点で極めて有益であり、かつ、追加するコンデンサ
は低容量のものでよいため、低コスト化ならびに省スペ
ース化に寄与し、リレー接点の応答にも別設の支障をき
たさない。
Effects of the Invention According to the present invention, when a rear-stage circuit is connected to a front-stage circuit together with a multi-winding latch relay to transmit a logic signal from the front-stage circuit to a rear-stage circuit, the induced electromotive force generated in the coil of the relay can be appropriately controlled. Because it can be suppressed accurately, it is extremely useful in preventing malfunctions in subsequent circuits, and since the additional capacitors only need to be of low capacity, it contributes to cost and space savings, and the response of relay contacts is also independent. It does not interfere with the installation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る実施例1の回路図、第2図は同回
路動作を示すタイムチャート、第3図は本発明に係る実
施例2の回路図、第4図と第5図は同回路動作を示すタ
イムチャート、第6図は本発明に係る実施例3の回路図
、第7図は本発明の前提となる回路図、第8図は同回路
動作を示すりイムチャートである。 1・・・・・・前段回路、2・・・・・・複巻線ラッチ
リレー、2a・・・・・・セットコイル、2b・・・・
・・リセットコイル、3・・・・・・後段回路、Da 
・Db・・・・・・第1ダイオード、D、、D2・・・
・・・第2ダイオード、C1、C2・・・・・・コンデ
ンサ。    ゛ 代理人の氏名 弁理士 中 尾 敏 男 ほか1名2−
a巻線うヅ弁リレー 20− セットコイル C1,Cp−コツナツプ 第2図 bL 第3図 第4図 bH 第5図 第6図
FIG. 1 is a circuit diagram of Embodiment 1 according to the present invention, FIG. 2 is a time chart showing the operation of the same circuit, FIG. 3 is a circuit diagram of Embodiment 2 according to the present invention, and FIGS. 4 and 5 are FIG. 6 is a time chart showing the operation of the same circuit, FIG. 6 is a circuit diagram of Embodiment 3 according to the present invention, FIG. 7 is a circuit diagram that is a premise of the present invention, and FIG. 8 is a time chart showing the operation of the same circuit. . 1... Pre-stage circuit, 2... Multi-winding latch relay, 2a... Set coil, 2b...
...Reset coil, 3...Late stage circuit, Da
・Db...First diode, D,, D2...
...Second diode, C1, C2... Capacitor.゛Name of agent Patent attorney Toshio Nakao and 1 other person2-
a Winding pipe valve relay 20 - Set coil C1, Cp - Kotsunap Fig. 2 bL Fig. 3 Fig. 4 bH Fig. 5 Fig. 6

Claims (1)

【特許請求の範囲】[Claims] 前段回路に複巻線ラッチリレーとともに後段回路を接続
する構成を備え、前記複巻線ラッチリレーのセットコイ
ルとリセットコイルには第1ダイオードを各々並列接続
し、前記コイルのうちの少なくとも前記後段回路に接続
される方のコイルには、前記第1ダイオードとは逆向き
の第2ダイオードを直列接続するとともにこのコイルと
前記第2ダイオードの直列回路にコンデンサを並列接続
したことを特徴とする複巻線ラッチリレーを含む信号伝
送回路の誤動作防止装置。
A configuration is provided in which a rear stage circuit is connected to the front stage circuit together with a multi-winding latch relay, and a first diode is connected in parallel to each of a set coil and a reset coil of the double winding latch relay, and at least one of the coils is connected to the rear stage circuit. A second diode having a direction opposite to that of the first diode is connected in series to the coil connected to the second diode, and a capacitor is connected in parallel to the series circuit of this coil and the second diode. Malfunction prevention device for signal transmission circuits including line latch relays.
JP63024337A 1988-02-03 1988-02-03 Malfunction prevention device for signal transmission circuits including double winding latching relays Granted JPH01200531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63024337A JPH01200531A (en) 1988-02-03 1988-02-03 Malfunction prevention device for signal transmission circuits including double winding latching relays

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63024337A JPH01200531A (en) 1988-02-03 1988-02-03 Malfunction prevention device for signal transmission circuits including double winding latching relays

Publications (2)

Publication Number Publication Date
JPH01200531A true JPH01200531A (en) 1989-08-11
JPH0580775B2 JPH0580775B2 (en) 1993-11-10

Family

ID=12135366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63024337A Granted JPH01200531A (en) 1988-02-03 1988-02-03 Malfunction prevention device for signal transmission circuits including double winding latching relays

Country Status (1)

Country Link
JP (1) JPH01200531A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4714635U (en) * 1971-03-17 1972-10-20
JPS5077742U (en) * 1973-11-19 1975-07-05

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4714635U (en) * 1971-03-17 1972-10-20
JPS5077742U (en) * 1973-11-19 1975-07-05

Also Published As

Publication number Publication date
JPH0580775B2 (en) 1993-11-10

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