JPH01200650A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing large-scale integrated circuits (LSI), particularly multilayer wiring.

[Conventional technology]

For example, FIGS. 6 to 11 are process flow diagrams for forming connections (contact holes) between a semiconductor substrate and interconnects and connections between multi-no interconnects (through holes) in conventional LSIs.First, as shown in FIG. Semiconductor substrate [1]
An IP3 film (2) is formed on top, and a resist (3) is coated and patterned as shown in FIG. 7, and the resist (3) is used as a mask by etching and drilling a contact hole. Then, as shown in Figure 8, add wiring material (4
) is deposited, and an insulating film is formed on the wiring material as shown in FIG.

A resist t31 k is applied and patterned again on the insulating film, and etching is performed using the resist as a mask to open a through hole. (FIG. 10) Then, as shown in FIG. 11, wiring material (4) is deposited. As described above, the steps are repeated to form contacts between the semiconductor substrate and the multilayer wiring.

[Problem to be solved by the invention]

In the conventional OL S I, 2 contact points between half 40,000 boards and multilayer wiring are formed as described above.

The more multilayer wiring there is, the more steps such as coating, patterning, etching, etc. become necessary, making the process more complicated.Moreover, there are problems such as poor flatness due to the formation of steps in the exposed areas.

This invention was made to solve the above-mentioned problems, and aims to simplify the molding process and form a multilayer wiring film with good flatness.

[Means to solve the problem]

The method of forming a connection between a semiconductor substrate and a multilayer wiring according to the present invention involves forming a laminated structure consisting of a wiring material and an insulating film, and then simultaneously etching the laminated layer to form a hole, and filling the hole with the wiring material.

[Effect]

In the present invention, by etching a multilayer wiring film and an insulating film and filling the holes with wiring material, the process is simplified and at the same time a wiring film with good flatness is formed.

〔Example〕

An example iy1gt diagram of this invention will be explained.

FIG. 1 is a diagram showing the connection between a semiconductor substrate (1) and a multilayer wiring film (4) according to an embodiment of the present invention. In the figure, +2) is an insulating film, and (51 is a contact hole/through hole filled with wiring material.

Figures 2 to 4 are diagrams showing the process up to f&6 in Figure 1. First, as shown in Figure 2, an insulating film (2) and a wiring material (4) are alternately deposited on the semiconductor substrate +11. Then, as shown in FIG. 23, a laminated film is formed, V-disk h+31k is applied, puttered/jung, and etched as a V-disk '1 mask to open holes to the required extent. Then, as shown in FIG.
t-embed. Then, as shown in FIG. 1, a wiring material is deposited on the insulating film and the buried layer.

A connection is made between the semiconductor substrate and the multilayer wiring film. If the multilayer wiring film and contact holes are formed in the flow shown in Fig. 2 → Fig. 3 → Fig. 4 → Fig. 1 in this way, the # manufacturing process can be simplified and a multilayer wiring film with good flatness can be obtained. .

Note that the above embodiments involve a semiconductor substrate and a multi-no wiring film.

In particular, the connection up to two-layer wiring will be described, but the invention may be applied to a wiring board with many layers, or may be applied only to connections between wires as shown in FIG.

Sarinima fc may be used to connect circuit quantities in three-dimensional circuit elements.

[Effects of the Invention] As described above, according to the present invention, connection is achieved by etching the insulating film and the multilayer wiring film and filling the holes with wiring material, which simplifies the process and at the same time creates wiring with good flatness. It has the effect of forming a film.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a method for connecting a semiconductor substrate and a multilayer film according to an embodiment of the present invention, and Figs. It is a diagram. FIG. 5 is an explanatory diagram of another embodiment of the invention. FIGS. 6 to 11 are explanatory diagrams of conventional process flows. In the figure, the opening 21 is a semiconductor substrate, and the opening 21 is an insulating film layer. (4) is a wiring material film, and +51 is a distribution material insertion layer. Note that the same reference numerals in Figure 1 indicate the same or equivalent parts.

Claims (1)

[Claims] The first step is to alternately stack an insulating film and a wiring material on a semiconductor substrate to form an insulating film on top. A resist is applied and patterned on the top insulating film, and the resist is used as a mask to form an insulating film on top. A second step of opening a hole in the wiring material by etching, a third step of filling the hole with the wiring material, and a fourth step of forming a wiring material film on the uppermost insulating film and the wiring material embedded layer. A method of manufacturing a semiconductor device including: