JPH01200662A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device whose operation margin is wide, whose access time is short and whose manufacture is easy by a method wherein a bit-line pair is composed of different wiring layers and is constituted in such a way that they are crossed at the middle point. CONSTITUTION:Aluminum wires as indicated by (A) and polycide wires is indicated by (B) are used as bit lines; they are crossed mutually at the central part of their length; they constitute a bit-line pair composed of a bit line 3a continued from polycide aluminum and a bit line 3b continued from aluminum polycide. Because a half L/2 of their total length (L) of the individual bit lines 3a, 3b is constituted by polycide, a total resistance value from a sense amplifier 5 to the farthermost end is equal in any bit line; the resistance value is about half that of a bit line whose length is composed of polycide. Due to the symmetry of the individual bit lines, a capacitance value CBB between the bit lines and an earth capacitance value CBO are equal at the individual bit lines; in addition, because the adjacent bit lines are situated in different layers, the distance between the lines is long; accordingly, the value CBB becomes extremely small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device using a bit line pair in a bit line portion, and hereinafter, a MOS type dynamic memory device.
This will be explained using random access memory (DRAM) as an example.

[Conventional technology]

Figure 2 shows a DRAM using the conventional folded bit line method.
This is a conceptual configuration diagram of the memory array section of (1).
) is a memory row decoder, (2) is a word line selected by row decoder 1, 3 is a bit line that intersects word line 2, and 4 is a memory provided at a required intersection between word line 2 and bit line 3. A cell 5 is a sense amplifier (abbreviated as a sense amplifier and includes an active restore circuit) that reads the contents of the memory cell 4 via the bit line 3. Note that Ca1l in the figure is the parasitic capacitance between the bit lines 3, and Cl
l0 is the ground capacity of Bifu Do Line 3.

In DRAMs up to 256 kbit, aluminum has been widely used as the wiring material for the bit line 3.
With the advent of IMbit, volicide bit lines have become mainstream. The reason for this is that when the memory capacity reaches IMbit, the bit line pitch becomes 4 μm or less, but in the case of aluminum wiring, the film thickness is reduced to about 1 μm or less, taking into account the wiring resistance of the peripheral circuit and the electromigration silicon. Since it cannot be made very thin, the above parasitic capacitance C@8
This is because the signal interference between the bit lines increases rapidly, and the operating margin is significantly impaired due to signal interference between the bit lines.

Since the film thickness of polycide can be reduced to about 0.3 μm, it has the effect of reducing the bit line width and widening the bit line spacing, reducing the line parasitic capacitance C at the IMbit level.
Since l1l+ is small (3% or less of the ground capacity C3°), the above problem does not occur. However, polycide has a higher wiring resistance than aluminum (up to 10" times), causing a delay in access time. This will be briefly explained using a diagram.

FIG. 3 is a diagram showing the timing of operation waveforms when reading a general RAM. During the precharge period, the bit line 3 is precharged and equalized. As shown in (a), at time t. The potential of the word line 2 rises, and the charge stored in the storage capacitor of the memory cell 4 is read out to the bit line 3. This read signal is pitch l-'f
As shown in (b), the signal begins to reach the node of the sense amplifier 5 at time t, and after reaching the node completely,
As shown in (C), the sense amplifier activation signal rises at time t2, thereby lowering the low (“L”) level bit h'A3 to Vss as shown in (bl).
level, and then the active restore activation signal causes the high (H”) level bit line 3 to drop to Vcc≠
The time it takes for the read signal from ≠4 to reach the sense amplifier 5, that is, it is determined by the resistance of bit vA3,
In the case of polycide bit lines, this time accounts for about one-fourth of the total access time, and this proportion is expected to increase as the degree of integration increases.

Here, the parasitic capacitance between the bit lines mentioned earlier ill CI+
The problem of signal interference due to No. 11 will be explained a little more. As shown in FIG. 3(a), after raising the potential of the word line 2, all the bit lines 3 are connected from the memory cells 4 to “H”.
゛When level information is read, the reference level bit line is sandwiched between the 'H' level bit lines, so it receives noise from the adjacent bit line due to the parasitic capacitance C1l!l between the bit lines. , the potential increases slightly, and
The "H" level bit line also receives the reaction, and the original "
Therefore, the read potential difference between the 3 pairs of bit lines becomes smaller and the read margin decreases.This means that when information at the "L" level is read out to all bit lines 3, It also happens.

[Problem to be solved by the invention]

Since the conventional DRAM is configured as described above, there is a problem that the capacitance between the bit lines greatly impairs the operating characteristics or increases the access time.

The present invention has been made to solve the above-mentioned problems, and its object is to provide a high-speed semiconductor memory device with low inter-bit line capacitance and low bit line resistance, that is, with good operating characteristics.

[Means to solve the problem]

A semiconductor memory device according to the present invention has a first line made of a first line material that has a low resistance but cannot be made very thin, and a second line material that has a relatively high resistance but can be made thin. The second line is lined up and electrically connected so that the two lines intersect three-dimensionally at a point half the length of the second line to form a bit line pair.

[Effect]

In the bit lines of the semiconductor memory device according to the present invention, adjacent bit lines are made of different line materials and are located in different wiring layers.
Since the line capacitance is small and half of the bit line length is made of the first line material with low resistance, it is easier to transmit read signals than a bit line made entirely of a general second line material. Since the bit lines of the bit line pair have exactly the same capacitance and resistance, malfunction of the sense amplifier does not occur.

〔Example〕

FIG. 1 (+11 is a schematic plan view showing a bit line portion of an embodiment of the present invention, and FIG. 1(b) is a schematic cross-sectional view taken along line I!I-1. The same reference numerals as those in the conventional example in the figure indicate equivalent parts. In this embodiment, as shown in the figure, the aluminum wire shown in A and the polycide line shown in A are used as the bit lines, and they intersect with each other at the center of their length. Connect and
Polycide-Aluminium followed by bit'b? 13a and aluminum polycide, forming a bit line pair consisting of the following bit line 3b. Polycide and aluminum may be used as they are to bridge the cross-connection portion, but aluminum and polycide may be connected using another wiring layer.

In FIG. 1 fat, half L/2 of the total length of each bit line 3a, 3b is made of polycide, so
The total resistance from the sense amplifier 5 to the farthest end is the same for all bit lines, and this resistance value is approximately half that of a bit line whose total length is polycide. Also, due to the symmetry of each bit line, the inter-bit line capacity ic++! +, ground-to-ground t
C9° is the same for each bit line, and since adjacent bit lines are located in different layers as shown in FIG. 1(b), the distance between the lines is long, and therefore C11fi is extremely small. Furthermore, the aluminum and polycide wiring pitches are twice the bit line pitch, making patterning easier during fabrication.

In the above embodiment, aluminum and polycide were used as the wiring materials for the bit lines, but the present invention is not limited to this, and other wiring materials may be used.

〔Effect of the invention〕

As described above, according to the present invention, the bit line pairs are constructed by using different layouts #1Ari and intersecting at the midpoint, so that the semiconductor memory device has a wide operating margin, short access time, and is easy to manufacture. It has the effect of obtaining.

[Brief explanation of the drawing]

FIG. 1(a) shows a dynamic R according to an embodiment of the present invention.
FIG. 1(b) is a schematic plan view showing the bit line portion of AM, and FIG.
This figure is a conceptual configuration diagram of a memory array section of a conventional dynamic RAM, and FIG. 3 is a timing diagram illustrating a read operation of the memory array section of a general dynamic RAM. In the figure, 2 is a word line, 3a is a first bit line, 3
b is a second bit line, b is an aluminum line portion, opening is a polycide line portion, and 4 is a memory cell. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A device having a plurality of bit line pairs each having complementary bit lines arranged adjacent to each other, a plurality of word lines intersecting the bit line pairs, and memory cells provided at required locations at the intersections, The bit line pair is composed of a first line and a second line disposed in the first and second layers, respectively, every other bit, and the first line has a low resistance but cannot be made very thin. The second wire is made of a second wire material that has a relatively high resistance but can be formed thinly, and the first and second wires are cut at the center of their length, a first and a second cross-connected to each other;
A semiconductor memory device comprising a bit line.