JPH01200720A - Analog counter circuit - Google Patents

Abstract

PURPOSE:To count lots of pulses with a few circuit components and to easily vary the count by forming the analog counter circuit through the connection of a voltage conversion circuit and a voltage comparator. CONSTITUTION:With an input terminal kept at L level to keep the counter in the ON state, when a clock phi1 changes from H to L and a clock phi2 changes from L to H, a potential of a connecting point between a source and a gate of a MOS transistor(TR) M1 rises, the drain potential is decreased, the TR M1 is turned off, a TR M0 turns on, and the charge is charged in a capacitor C1 from the power supply V1. If the level of the clocks phi1, phi2 changes opposite, the TRs MO:M2 are turned off and the TR M1 is turned on to charge a capacitor C2 by the charge of the C1. The electric charge is transferred one after another through the repetition of the processing above to charge up a capacitor C7, resulting in increasing the noninverting input level of a voltage comparator A. When the level reaches a reference voltage V2 or over, the comparator A is operative and its output level changes from L to H. As a result, TRs M7-M13 are turned on, the electric charge charged in the capacitors C1-C7 is discharged, the level of the output terminal of the comparator A changes from H to L thereby enabling itself to count clocks.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to analog counter circuits.

[Conventional technology]

Conventionally, this type of counter circuit has used an asynchronous digital counter in which the output terminal of the seven lip-flops in the previous stage is connected to the clock terminal of the seven lip-flops in the next stage. Up counters and down counters can be configured depending on the flip-flops used, and by obtaining the inverted AND of the outputs of the flip-flops and connecting that output to the reset terminal, it is possible to specify how many cycles pulses are output. I was able to do that.

[Problem that the invention seeks to solve]

The conventional digital counter described above is constructed by connecting flip-flops, and performs counting by latching the rising edge and falling edge of the pulse. If the maximum number of pulses that can be counted is Da and the number of flip-flops is N, then the maximum number of pulses that can be counted can be obtained by the equation (1).

m = 2”・・・・・・・・・・・・・・・・・・
(1) Therefore, there is a drawback that the number of circuit elements increases when there are many numbers to be counted. In addition, when changing the number to be counted, the output terminal of each flip-flop was connected to a selector circuit, and the circuit configuration was such that the selector circuit selected the number to be counted, making it easy to change the number to be counted with a small number of circuit elements. It also has the disadvantage of not being able to.

An object of the present invention is to provide a circuit suitable for configuring a counter with a small number of circuit elements and for easily changing the number to be counted.

Therefore, the present invention is configured by connecting a voltage converter circuit and a voltage comparator, in contrast to the above-described conventional digital counter configured by connecting a flip 70 tab, so that counting can be configured with fewer circuit elements. However, the difference is that the number to be counted can be easily changed.

[Means for solving problems]

One end of the first capacitor is connected to the source and gate of the first MOS transistor, and the other end of the first capacitor is connected to the first and second MOS transistors having a phase difference of 180 degrees.
is connected to one of the clocks of the second MO
The drain of the S transistor is connected to the source of the first MOS transistor and the gate ρ, and the source of the second MOS transistor is connected to a second power supply line. The source and gate of the first MOS transistor constituting the circuit are connected to the drain of the MOS transistor of the preceding partial circuit, and the first and second MOS transistors are connected to the drain of the MOS transistor of the preceding partial circuit, and The drain of at least one third MOS transistor is alternately supplied with a clock signal and has its source and gate connected to a predetermined voltage source, and the drain of at least one third MOS transistor is connected to the source and gate of the first MOS transistor of the first stage subcircuit. The drain of the first MOS transistor of the partial circuit of the last stage is connected to one of the second capacitors, the input of the voltage comparator, and the drain of the fourth MOS transistor, respectively, The other MOS transistor and the source of the fourth MOS transistor are connected to the second power supply line, the output of the voltage comparator is connected to the output terminal and the input of the OR circuit, and the input signal from the input terminal and The output of the OR circuit inputted with the output of the voltage comparator is connected to the gate of the fourth MOS transistor and the gates of the second MOS transistors of the plurality of partial circuits.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention, and FIG. 2 is a circuit diagram showing the configuration of a partial circuit of FIG.

The circuit of the present invention is composed of a booster circuit section and a voltage comparator section, and the booster circuit section includes one capacitor and two N-channel M
It has a cascaded circuit of six stages of partial circuits each consisting of O8 transistors.

Looking at FIG. 2, one end of capacitor C1 is connected to N-channel M
connected to the source and gate of the OS transistor M1;
The other end of the capacitor C1 is connected to one of the clock chains 2 having a phase difference of 180 degrees.

Further, a partial circuit is formed in which the drain of the N-channel MOS transistor M7 is connected to the source and gate of the N-channel MOS transistor M1, and the source of the N-channel MO8 transistor M7 is connected to the ground terminal GND.

The source and gate of the N-channel MOS transistor M1 constituting the partial circuit in FIG. 2 are connected to the drain of the N-channel MOS transistor in the previous partial circuit, and the drains of the N-channel MO8 and transistor M1 are
The even-numbered S transistors φ1 are connected to the clock φ2.

- Minohoshi Horei 4 Taka Looking at Figure 1, the source and gate of the N-channel A/MOS transistor Ml of the first stage partial circuit are connected to the drain of the N-channel MOS transistor MO, and the source of the N-channel MOS transistor MO and the gate are completely connected to the power supply terminal Vl. The drain of the N-channel MO8 transistor M6 of the last stage partial circuit is connected to one of the capacitor C7, the input to the voltage comparator, and the drain of the N-channel MO8 transistor M13, and the other of the capacitor C7 and the N-channel MOS transistor M13 are connected to each other. The source of is connected to the ground terminal GND. The output to the voltage comparator is connected to the output OUT of this analog counter circuit, and the output of voltage comparator A and the input terminal E of this analog counter circuit are connected to the input side of the OR circuit. The output terminal of is N channel M
It is connected to the gates of OS transistors M7 to M13.

When set to , the counter operation stops. Keep the input terminal low and keep the counter on, clock 1251...
When the clock 5212 changes from low level to low level, the potential at the connection point between the source and gate of the MOS transistor M1 in the first stage partial circuit is lowered, and the potential at the drain is raised. , N-channel MO8) When the transistor M1 becomes non-conductive, the N-channel MO
The S transistor MO is conductive and the charge is transferred to the N channel MOS.
From the power supply Vl through the transistor MO to the capacitor CI
is charged. Next, when clock 1 goes low level to low level and clock 2 goes from high level to low level, N-channel MO8 transistor MO-M2
becomes non-conductive, N-channel MO8I-transistor M1 becomes conductive, and capacitor C2 is charged by the charge of capacitor C1. By repeating this operation, charges are transferred one after another, and finally, capacitor C7 is charged, and voltage comparator A
The positive input potential of increases.

By operating the clock S, - in this way,
Voltage comparator AK generates a high voltage by sucking up charges from the semiconductor substrate on which the power supply and circuit are formed, and the voltage at the positive input terminal of voltage comparator A is applied to the negative input terminal of voltage comparator A. When the voltage reaches a voltage equal to or higher than the reference voltage source 72 (which is currently being used), voltage comparator A operates and the output of voltage comparator A changes from low level to high level. As a result, N-channel MOS transistors M7-M13 become conductive, the charges stored in capacitors C1-C7 are discharged, and the output terminal of voltage comparator A changes from high level to low level, allowing clocks to be counted.

The above explanation was made using an N-channel MO8 transistor, but
It can also be configured with a P-channel MOS transistor by reversing the polarity of the power supply and input/output.

FIG. 3 is a circuit diagram showing the configuration of a second embodiment of the present invention.

In the second embodiment, the drains of N-channel MOS transistors M14 and M2S are connected to the drain of an initial potential setting transistor MO, and the drains of N-channel MOS transistors M14 and M2S are connected to the drain of an initial potential setting transistor MO.
The source of the N-channel MOS transistor M15 is connected to the third power supply terminal V3, and the source of the N-channel MOS transistor M15 is connected to the third power supply terminal V4.
-The gates of M14 and M2S are connected to the output of selector B, and the select terminal C of selector B has a different configuration from the first embodiment.

In this circuit, one of the N-channel MO8 transistors MO, M14, and M2S is selected by input to the select terminal C. And the power terminal
1・V3. -N channel MO from either voltage of V4
By applying a voltage dropped by the threshold voltage of the 8' transistor to the source and gate of the N-channel MOS transistor M1, there is an advantage that the number of pulses to be counted can be easily changed.

〔Effect of the invention〕

As explained above, the present invention has the advantage of being able to count many pulses with a small number of circuit elements by using this analog counter circuit, and can be easily changed by changing the reference voltage of the voltage comparator. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the partial circuit of FIG. 1, and FIG. 3 is the configuration of the second embodiment of the present invention. A circuit diagram showing. vl・v3・■4...Power terminal, ■2...
・・Reference voltage source, ・5251-φ2・・・・・・Clock terminal, Cl-C7・=−capacitor, MO~M1
5.--N-channel MOS transistor, A...
...Voltage comparator, B...Selector, C...
...Select terminal, D...Order circuit, E
...Input terminal, RTN...Feedback terminal. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] One end of the first capacitor is connected to the source and gate of the first MOS transistor, and the other end of the first capacitor is connected to the first and second MOS transistors having a phase difference of 180 degrees.
is connected to one of the clocks of the second MO
The drain of the S transistor is connected to the source and gate of the first MOS transistor, and the drain of the S transistor is connected to the source and gate of the first MOS transistor.
The source of the transistor is constituted by a plurality of partial circuits connected to a second power supply line, and the source and gate of the first MOS transistor constituting the partial circuit are connected to the drain of the MOS transistor of the preceding partial circuit. and the drain of the first MOS transistor is connected to the source and gate of the next stage MOS transistor, and the first and second clock signals are alternately applied to the cascade-connected partial circuits according to the order. at least one third MOS transistor whose source and gate are connected to a predetermined voltage source is connected to the source and gate of the first MOS transistor of the first stage subcircuit; The drain of the first MOS transistor of the subcircuit of the stage is connected to one of the second capacitors, the input of the voltage comparator, and the drain of the fourth MOS transistor, respectively, and the drain of the first MOS transistor of the subcircuit of the stage The source of the MOS transistor No. 4 is connected to the second power supply line, the output of the voltage comparator is connected to the output terminal and the input of the OR circuit, and the input signal from the input terminal and the voltage comparator are connected to each other. An output of the OR circuit inputted with the output of is connected to the gate of the fourth MOS transistor and the gates of the second MOS transistors of the plurality of partial circuits.