JPH01200853A - Burst signal completion detecting circuit - Google Patents

Abstract

PURPOSE:To surely detect the completion of a burst signal regardless of the number of bits of the burst signal, etc., by executing a prescribed processing to the inputted burst signal by means of a burst signal completion detecting circuit. CONSTITUTION:For the burst signal, the waveform is shaped by a circuit 1. For the signal, the envelope is extracted by a circuit 2. The signal waveform is smoothed, by a circuit set at a prescribed limit level, at the limit level, and the waveform is made into the signal waveform which rises at the time of the start of the burst signal and starts to fall at the time of the completion of the burst signal. By a circuit 4 set at threshold indicated by a dotted line, a signal, which falls at the time of the rise start of the signal and sharply rises when the signal starts to fall, is outputted. A circuit 5 outputs the pulse of 1 shot when the output signal of the circuit 4 rises. In such a way, regardless of the number of bits of the input burst signal, the pulse of 1 shot can be outputted at the time of the completion of the burst signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a burst signal end detection circuit. More specifically, the present invention relates to the configuration of a novel burst signal end detection circuit that can reliably detect the end of a valid burst signal regardless of an error in the number of bits of the burst signal or the number of counted bits.

Conventional technology In the burst signal transmission method widely used in LAN and computer-to-computer communication, the number of bits forming one group of burst signals is determined in advance between the transmitter and the receiver, and the receiving side determines the number of bits of the received burst signal. The completion of reception of the burst signal is detected when the number of bits reaches a predetermined number.

Problems to be Solved by the Invention However, in the conventional system as described above, when attempting to transmit burst signals with different numbers of bits, it becomes necessary to change the setting of the number of bits in the entire system.

Further, an error may occur in the bit number counting process as described above, and in this case, it is not possible to accurately detect the end of the burst signal.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a novel circuit that solves the problems of the prior art described above, can handle a variable number of bits, and can reliably detect the end of a burst signal.

Means for Solving the Problems According to the present invention, a first circuit extracts from an input burst signal an envelope that changes in accordance with at least the start and end of input of the burst signal; a second circuit that compares the output of the circuit with a predetermined description level and outputs the result; and a third circuit that outputs a one-shot pulse when the comparison signal changes corresponding to the end of the burst signal based on the comparison result. A burst signal end detection circuit is provided.

Operation The burst signal end detection circuit provided in accordance with the present invention reliably detects the end of a burst signal, regardless of the number of bits of the burst signal, by performing predetermined processing on the input burst signal. This is the main feature.

That is, in the circuit according to the present invention, first, an input signal is shaped into a predetermined amplitude, the envelope of the input signal is extracted by a peak hold circuit, and the output of the peak hold circuit is further set to a predetermined limit level. By inputting it to the limiter, a signal is generated that is at a high level while a burst signal is input, and changes to a low level when the signal is no longer input. Furthermore, a circuit containing the output of a comparator that compares this signal with an appropriate threshold value allows outputting a one-shot pulse that rises at the end of the burst signal.

The burst signal end detection circuit according to the present invention configured as described above operates regardless of the number of bits of the burst signal, so it can be reliably operated regardless of the change in the number of input bits or the result of counting the number of input bits. The end of the burst signal can be detected.

The present invention will be described in more detail below with reference to the drawings, but what is disclosed below is only one embodiment of the present invention and does not limit the technical scope of the present invention in any way.

Embodiment FIG. 1 is a block diagram showing the basic configuration of a burst signal end detection circuit according to the present invention.

That is, in the circuit according to the present invention, first, a circuit 1 that amplifies an input signal to a predetermined amplitude, a peak hold circuit 2 that extracts an envelope of the input signal, and a predetermined limit level are set. a comparator circuit 4 that compares the output of the limiter circuit 3 with a predetermined threshold value to determine the magnitude of the input value; The display circuit 5 includes a display circuit 5 that outputs shot pulses.

FIGS. 2(a) to 2(f) are diagrams illustrating signal waveforms processed by each circuit as described above for each input or output of each circuit.

First, when a burst signal with a waveform as shown in FIG. 2(a) is input to the circuit 1, the input signal waveform is shaped so that the processing in the subsequent stage can be carried out effectively. The signal will be as shown.

The envelope of this signal is extracted in the circuit 2, resulting in a signal waveform as shown in FIG. 2(C). Furthermore, this signal waveform is smoothed by a circuit 3 set with a predetermined limit level as shown by the dotted line in FIG. 2(C), and a burst signal as shown in FIG. 2(d) is generated. The signal waveform rises at the start of the burst signal and begins to fall at the end of the burst signal.

In the circuit 4 in which the dark value is set as shown by the dotted line in FIG. 2(d), the signal shown in FIG. 2(d) falls when the signal starts to rise, and when this signal starts to fall, Outputs a rising signal. The circuit 5 outputs one shot pulse when the output signal of the circuit 4 rises.

Thus, regardless of the number of bits in the input burst signal as shown in FIG.
The shot pulse is output.

Specifically, a circuit having the above functions can be configured as follows, for example.

FIG. 3 is a circuit diagram showing a specific configuration example of the burst signal end detection circuit according to the present invention as described above. In FIG. 3, the circuits surrounded by dotted lines and given reference numbers 1 to 5 correspond to circuits 1 to 5 shown in FIG. 1, respectively.

The circuit 1 includes a comparator 6 set with a comparison reference level Vbl.
is formed by. Here, the comparison standard level Vb
l is set between the high level and low level of the input burst signal, and by comparing the input burst signal as shown in FIG. 2(a) with this comparison reference level Vbl, the value shown in FIG. A signal with a constant amplitude corresponding to the input signal is output as shown in b).

The circuit 2 is a peak hold circuit composed of a comparator or an operational amplifier 7, a capacitor 9 and a resistor 8 each having one end connected to a voltage source Vb2. Here, the output of the circuit 1 is coupled to the positive phase input of the operational amplifier 7, and the output of the operational amplifier 7 itself is coupled to the negative phase input to form negative feedback. Therefore, this circuit 2 holds the peak of the input signal according to the time constants of the capacitor 9 and resistor 8. Therefore, the output signal of the circuit 2 has a waveform as shown in FIG. 2(C).

Circuit 3 includes voltage sources Vb3 and V that set the bias level.
The output of circuit 2 is connected to the base of transistor 10, and the output of circuit 3 is connected to the base of transistor 10 and diode 11. It is taken out from between. In this circuit, the signal voltage above a predetermined voltage level is clamped to the diode 11, so the output voltage of the circuit 3 is limited to below a preset limit level, and thus the output voltage as shown in FIG. 2 (6) is limited. A signal is output.

The circuit 4 is formed by a comparator 12 to which a reference voltage vbs slightly lower than the limit level of the circuit 3 is input to the positive phase input, and by inputting the output signal of the circuit 3 to the negative phase input, the burst A signal having a waveform as shown in FIG. 2(e) which falls at the start of the signal and rises at the end of the burst signal is output.

The circuit 5 is constructed by adding a diode 15 and a resistor 16 to a differentiator circuit consisting of a capacitor 13 and a resistor 14. The differentiating circuit outputs negative and positive pulses at the rise and fall of the output signal of the circuit 4, respectively. Since the diode 15 passes only the positive pulses among these pulses, one shot of pulse is output from the circuit 5 only at the end of the burst signal, as shown in FIG. 2(f). In addition, a resistor 1 whose one end is grounded
6 is the output resistance of this circuit.

Effects of the Invention As detailed above, the burst signal end detection circuit according to the present invention detects the end of a burst signal regardless of the number of bits of information carried by the burst signal. That is, since the burst signal end detection circuit according to the present invention does not depend on the number of bits of the burst signal in its operation, it is possible to detect the end of the burst signal even if the number of bits of the signals constituting the burst signal changes. Can be done.

Further, unlike the conventional burst signal end detection method, processing such as counting the number of bits of the received burst signal is not performed, so there is no possibility of inaccurate end detection due to an error in counting the number of bits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the basic configuration of a burst signal end detection circuit configured according to the present invention, and FIGS. 2(a) to (f) show the burst signal end detection circuit shown in FIG. 3 is a diagram illustrating signal processing in each component of the circuit, and FIG. 3 is a circuit diagram showing a specific example of the configuration of the burst signal end detection circuit shown in FIG. 1. FIG. [Main reference numbers] 6.12・・・・・・Comparator, 7・・・・・・・・・Operational amplifier (comparator), 8
．． 14.16...Resistor, 9.13...Capacitor, 10...
...... Transistor, 11.15...
...Diode patent applicant Sumitomo Electric Industries, Ltd.

Claims (4)

[Claims] (1) A first circuit that extracts an envelope that changes from an input burst signal at least in response to the start and end of input of the burst signal, and sets the output of the first circuit to a predetermined description level. a second circuit that compares and outputs a result;
Based on the comparison result, a third pulse is output at a time when the comparison signal changes corresponding to the end of the burst signal.
A burst signal end detection circuit comprising a circuit. (2) The burst signal end detection circuit according to claim 1, wherein the first circuit includes a peak hold circuit that detects an envelope of the input burst signal. (3) The burst signal end detection circuit according to claim 1 or 2, wherein the first circuit includes a circuit for waveform shaping an input signal to the first circuit. . (4) Any one of claims 1 to 3, wherein the first circuit includes a limiter circuit that limits the output signal of the first circuit to a predetermined limit level.
The burst signal end detection circuit described in .