JPH01201176A - Resetting method for logic circuit - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of resetting a logic circuit, that is, a method of setting an initial value.

2. Description of the Related Art In conventional logic circuits, all logic blocks are uniformly reset by a common reset signal. In particular, when testing logic circuits, it is necessary to be able to control the input signals of each block in order to test and debug the functions of the logic blocks individually. FIG. 4 shows inputs 3, 4, . . . of logic block 1 to be tested using the scan path method.
5 is given not from the outputs 6, 7.8 of the surrounding logic blocks 2, but from the outputs of flip-flops 9, 10, and 11. The flip-flops form a shift register, Input data for the block 1 is shifted in from the serial input terminal 13 in synchronization with the shift clock 12.The output of the flip-flop can be set to the "H" level by setting the select signal 17 of the multiplexer 14, 15, 16 to the "H" level. The input signal is applied to block 1 to be tested. Now that the input signal setting is complete, next set the reset signal 18 to the "L" level and initialize the block 1, and then set the reset signal 18 to "
When the reset is released by setting the block to H'' level, the block 1 generates one output in response to the input signal from the flip 70 tube. Therefore, by observing this output 19, it is possible to judge whether the block is good or not.

Problems to be Solved by the Invention In such conventional logic circuits, the logic blocks have a common reset signal, so when a logic block is tested after being reset, input signals from surrounding logic blocks must be reset. Since it is released, the initial value cannot be held, so a scan path flip-flop must be provided so that all input signals can be controlled.

In particular, when testing a logic block with a large number of input signal lines, the number of required gates increases, resulting in a large-scale test circuit.

The present invention has been made in consideration of these points, and the present invention uniquely determines the value of the input signal line of the logic block to be tested by a simple means, and the number of input lines to be controlled by the flip-flop is determined. 3. Means for Solving the Problem The present invention solves the above problems by selecting a logic block and a clock generation circuit to be tested from among logic blocks constituting a logic circuit. A means for canceling the reset is provided, and the reset signal is enabled for other logic blocks.

Operation According to the present invention, with the above-described configuration, since the surrounding logic blocks are in a reset state, the signal line supplied therefrom to the logic block to be tested is initialized and held at a constant value. Therefore, it is possible to reduce the number of signal lines required for logic block testing, that is, the number of signal lines to be controlled using scan path flip-flops.

Example Hereinafter, one embodiment of the present invention will be described based on the drawings.

In FIG. 1, the logic block 1 to be tested has a reset terminal 20, and the surrounding logic blocks 2 also each have a reset terminal 21,22. During testing, the reset terminals 21 and 22 are enabled and turned off, while the reset terminal 2 of the logic block 1 to be tested
o is disabled. In this case, among the outputs 6 and 7.8 from the surrounding logic blocks, the initial value of output 6 can be used as an input signal for block 1 to be tested, so output 6 can be used as a scan path as shown in output 8. There is no need to provide flip-flops 10.11. In other words, the scan path circuit for testing can be simplified.

FIG. 2 shows a block configuration in the case where logic block 1 to be tested in the entire logic circuit is tested using the scan path method. To each surrounding logic block 2,
Reset signal lines 20 to 2 respectively in the reset circuit 25
4 is supplied, and a reset signal 23 is also input to the clock generation circuit 26.

FIG. 3 shows a logic diagram of the reset circuit 25 as an example. When the select enable SE is "L", when a reset is applied, that is, when RESET becomes "L", each logic block and clock generation circuit are activated. Since the connected reset signals 20 to 24 are enabled, the entire circuit is reset. Next, when SE is set to "H", the reset of the clock generation circuit 26 is released and the clock is supplied by the entire logic circuit.In addition, the reset signal specified by the selection terminals so and Sl of the block is " Since "L" changes to "H" (becomes disabled), the reset of the logic block specified by s, , and Sl is released.In this case, sl is set to "H" and s.

When set to "L", the reset signal 2o becomes "H", so the reset of logic block 1 is canceled, and the output signal value to logic block 1 to be tested is set while the surrounding logic block 2 is reset. can be initialized, making it easy to perform functional tests using scan paths.

Effects of the Invention According to the present invention, since it is possible to easily determine the value of the signal of the logic block to be tested, the test circuit can be simplified accordingly. Therefore, it is extremely effective as a reset method for large-scale logic circuits with a large number of input signal lines.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a logic circuit reset method in an embodiment of the present invention, FIG. 2 is a block diagram for explaining the method in more detail, FIG. 3 is a logic diagram showing the reset circuit, and FIG. 4 is a block diagram of a conventional reset method. 1...Logic block to be tested, 2...
... Surrounding logic blocks, 3 to 5 ... Inputs to logic blocks, 9 to 11 ... Flip-flops for scan path, 20 to 24 ... Reset signal, 25 ...Reset circuit. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2 Tsuya Z To Enroya,

Claims (1)

[Claims] In a logic circuit consisting of a plurality of logic blocks, all reset terminals of the logic blocks are enabled to achieve a reset state of the entire circuit, and then only the reset terminal of the selected logic block is disabled to achieve the reset state of the logic block. 1. A method for resetting a logic circuit, comprising releasing a reset state, initializing input signal values from surrounding logic blocks, and testing the logic block.