JPH01201766A - Logical simulator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a logic simulation device that simulates the operation of a logic circuit.

Conventional technology logic simulation refers to simulating what kind of output is obtained when a certain input is applied to a logic circuit. Therefore, in the process of executing logic simulation, the output state of each logic gate constituting the logic circuit is determined from the input state.

Logic simulation typically deals with events that indicate changes in the state of logic gates, including information about the identity of the logic gate, information about the state of the logic gate, and information about the time at which this state occurs. This event occurs as the logic simulation is executed and is stored in the event memory.

Determining the state of the output from the state of the input of the logic gate is performed by the evaluation means. Here, from the input state of the logic gate, the logic type of the logic gate, the signal delay time of the logic gate, etc., we calculate the state and time when the output state of the logic gate reaches the state that the output state of the logic gate reaches as the input state changes, and then calculate If the current state of the logic gate and the event of this logic gate are in the event memory, an appropriate event is created from the state and time and is stored in the event memory. Note that the state of the output of the logic gate and the state of the logic gate are the same.

The procedure for creating an event in the evaluation means described above is complicated. This will be explained using FIG. 7.

Now, a NAND gate with a signal delay time td having an input person, an input B, and an output Y shown in FIG. 7 (Δ) in FIG. 7)
Consider the case where the signal shown in is applied. Input person is in state 1
continues, and input B changes from state ○ to state 1 at time to
Changes to

Now, since the input states A and B are both 1 at time to, there is a signal delay t (after 1, that is, time ty
, the output Y must be in state 0. Here, since the state of output Y at time to is 1, a change in the state of output Y occurs at time ty, and an event is created and stored in the event memory. This event is
This information includes time ty and state 0.

If the state of output Y does not change, no event is created.

Next, as shown in FIG. 7(C), the input signal changes from state 1 to state 0 at time t^, and input B changes from state 0 to state 1 at time tB, such that ta tn<ta. Consider the case where is applied.

At time tB, as in the case of FIG. 7 (IL), an event in which the output Y becomes 0 at time tY, =tB+td is created and stored in the event memory.

At time tA, the input cam is in state 0, so the output Y must be in state 1 at time ty2 = tA+t(1).

Now, at time tA, the output Y of ty, )tm remains in state 1. Therefore, at time tA, the output Y will not change its state at time tY2, and no event will be created. As a result, the output Y is at time t
After y+ reaches state 0, it does not change, resulting in a contradiction. For this purpose, at time tm, the event memory is searched to find the event of output Y at time tY, and this is compared with time tY2 and the state that output Y reaches at time tY2, and the state at time tY2 is A decision must be made to create one event and store it in the event memory.

Moreover, the state of the output Y shown in FIG. 7(0) is at time tY
1, the input person becomes state 0 at time tA before it becomes state 0. Therefore, it is difficult to imagine that the output Y will be in the open state 0 between times ty+ and tY2, and the open state should be indefinite between times ty and tY2, as shown by Y' in FIG. 7(C). In this case, at time tB, state 0 at time ty
Since the event in the event memory is stored in the event memory, at time tA, the event in state 0 at time ty is deleted, and the event in state 1 at time ty1 and the event in state 1 at time tY2 are created. Must be stored in memory.

The event creation procedure described above is just one example; the current state of the logic gate, the output state calculated from the input state, the time to reach that state, and even the event of this logic gate exist in the event memory. It is necessary to process many combinations of the status and time, etc., so that there are no contradictions, and the procedure is extremely complicated.

Further, the event creation procedure is an essential process for executing a logical simulation, and requires a lot of time.

Problems to be Solved by the Invention In conventional logic simulation machines, the above-described event creation procedure was sequentially processed using a microprogram or the like. For this reason, a lot of time is required for processing, which causes a decrease in the execution speed of logical simulation.

In addition, there was a method in which the event creation procedure was executed by circuit means, but the configuration of the circuit means was complicated and the execution speed was therefore slow.

Means for Solving the Problems The present invention has been made in view of the problems that existed in the conventional logic simulation machines mentioned above. a logical simulation comprising: an evaluation means for executing a logical operation, creating an event, and storing it in the event memory; and a memory means storing information for controlling the storage of the event in the event memory by the evaluation means. In the apparatus, the memory means stores the current state of the logic gate, the state of the event of the logic gate obtained by calculation by the evaluation means, and whether the event of the logic gate is stored in the event memory. , the state of the event of the logic gate if it is stored in the event memory, the time of the event of the logic gate obtained by the operation, and the event of the logic gate stored in the event memory. The address input is data that includes data indicating the magnitude of the time of the event, and data indicating whether or not to erase the event of the logic gate stored in the event memory, and the data is stored in the event memory. an event state of the logic gate, and data specifying, as the time of the event, the time of the event of the logic gate obtained by the logic operation or the time of the event of the logic gate stored in the event memory; This is a logic simulation device characterized in that it is a memory means that outputs data including data as information.

Operation The present invention is equipped with a memory means that stores information on how to perform an event creation procedure, and stores information on the current state of logic gates necessary for the event creation procedure and this logic calculated by the evaluation means. The memory means is accessed using the state of the gate, etc. as an address, and data such as the state of the event related to the creation of the corresponding event and whether or not to erase the event of this logic gate in the event memory are read out. Therefore, the configuration of the means for executing the event creation procedure can be simplified and the speed can be increased.

, Embodiment The first embodiment of the logic simulation machine according to the present invention is described below.
As shown in the figure. Here, 1 is event memory, 2 is evaluation means,
3 is a control memory. Further, 4 is an element table.

The event memory 1 stores events that occur as a logic simulation is executed.

The evaluation means 2 accesses the event memory 1, the control memory 3, and the element table 4, and executes a logic simulation. At this time, the procedure for creating the event mentioned above is as follows.
The control memory 3 is accessed and determined.

The control memory 3 stores the current state of the logic gate, the evaluation means 2
The state of this logic gate calculated from the state of the input in , and information such as the state if there is an event of this logic gate in event memory 1 are used as address inputs, and information such as the state and time of the event to be stored in event memory 1 is input. It is a memory means that outputs information as data.

The element table 4 stores connection information and states of logic gates constituting a logic circuit.

Reference numeral 6 denotes an address bus and a data bus through which the evaluation means 2 accesses the control memory 3.

The bus 5 is constructed as shown in FIG.

where 3CI and SCO are the current states of the logic gates,
Se1 and Seo indicate the states of the logic gates calculated by the evaluation means 2. As shown in FIGS. 3(a) and 3(b), these are allocated so that each state is represented by 2 bits.

Also, Txl and TxO, TH1 and THOlTL
1 and TLO indicate the presence or absence of an event of the logic gate in the event memory 1, and represent the data shown in FIG.

The aforementioned Sc, Se, TX, TH, and TL serve as address inputs to the control memory 3.

Sx, SR, and St, respectively indicate an event in which the state is indeterminate, state 1, and state 0 are stored. When instructing to store events in state 1 and state O, the evaluation means 2 uses the time obtained by calculating the signal delay time of the logic gate as the event time. When instructing to store an event with an indeterminate state, the event time is Tsl and rso
specified by.

Tgl and .tau.SO specify the time of an event as shown in FIG. 6 when an instruction is given by Sx to store an event with an undefined state.

Ux, UH, and UL instruct to erase events of undefined state, state 1, and state 0 of the logic gate stored in event memory 1, respectively.

Now, the control memory 3 has Sc, Se, Tx,
TH and TL SX, SR, and TL explain how to perform the event creation procedure for different addresses.
S.L.

Since it is to be output to UX, UH, UL, and TS, necessary data must be stored.

FIG. 6 shows part of the data stored in the control memory 3. This is the output Y' shown in Figure 7(C).
This is the data when obtaining . In reality, data must be stored for all necessary addresses among input addresses.

The procedure for creating an event using the data shown in FIG. 6 will be described below.

First, since the state of the logic gate is state 1 at time t in FIG. 7(C), (Sal, 3co)=(1, 1). Since the waiting cam is in state 0 and the human power B is in state 1, the evaluation means 2 calculates and obtains that the output Y will be in state 1 at time tY2. That is, (Se1.5eO)=(1,1).

Now, when the event memory is searched, it is found that there is only one event for the logic gate, which is in state 0 and at time ty+.

ty+ (tyz Because it is (TXl, TKO) = (0, O) (THl, THO) = (0,0) (TLl, TLO) = (1, O) becomes.

If the control memory 3 is accessed using the data obtained above as an address, 5x=1, 5H=1, 5L=O trx=o, UH==O, UL=1 (TSl,
T! ! O) = (0, O) is obtained as data.

Therefore, the state of the logic gate in event memory 1 is 0.
erase the event of the logic gate, state 1 time tY2 of the logic gate
and the event of the state of the logic gate at an undetermined time tY are stored in the event memory 1.

The procedure for creating an event in this way is
This is obvious just by accessing control memory 3.
It's easy and fast.

In this manner, a logic simulation can be executed to obtain the output Y' shown in FIG. 7(C).

It should be noted that the configuration of the bus 5 shown in this embodiment and FIGS.
The assignments and meanings of the data shown in the figures do not necessarily have to be the same as in the embodiments, but may be the most appropriate for configuring the logic simulation machine.

However, the bus 5 is most suitable when configured as shown in this embodiment.

Effects of the Invention As can be seen from what has been described above, the logic simulation machine according to the present invention can easily and quickly perform the complicated and time-consuming event creation procedure.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a logic simulation device according to the present invention, FIG. 2 is a block diagram illustrating some of the components of the embodiment in more detail, and FIGS. 3 and 4 and FIG. 6 is an explanatory diagram illustrating an example of data allocation of the same component, and FIG. 6 is a configuration diagram showing part of the data stored in the control memory shown in FIGS. 1 and 2.
FIG. 7 is a timing diagram illustrating processing when executing a logic simulation. 1...Event memory, 2...Evaluation means, 3...Control memory, 6...Bus. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 5 Figure 6

Claims (1)

[Claims] an event memory that stores events that occur when a logic simulation is executed; an evaluation device that executes a logical operation of a logic gate to create an event and stores it in the event memory; and an event memory that stores the event in the event memory by the evaluation device. a logic simulation device comprising: memory means storing information for controlling storage of the logic gate;
The state of the event of the logic gate obtained by the calculation by the evaluation means, the information indicating whether the event of the logic gate is stored in the event memory, and the event of the logic gate stored in the event memory. If so, the state thereof, the time of the event of the logic gate obtained by the logic operation, and data indicating the magnitude of the time of the event of the logic gate stored in the event memory, as information. as an address input, and data indicating whether or not to erase the event of the logic gate stored in the event memory, the state of the event of the logic gate to be stored in the event memory, and the state of the event at the time of this event. and a time of an event of the logic gate obtained by the logical operation, or data specifying the time of the event of the logic gate stored in the event memory, as data output. A logic simulation device characterized by the following.