JPH01201937A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device, and in particular to a beam, 1. High voltage bipolar element or high voltage double diffusion type M
O5) Transistor (Double DiffusedM
O5Tr. The present invention relates to a semiconductor device in which a low breakdown voltage bipolar element (hereinafter abbreviated as DMO5) and a low breakdown voltage DMO3 are formed on the same substrate.

<Conventional technology> Conventional glue, 1. FIG. 4 shows an example of a semiconductor device in which a high breakdown voltage element and a low breakdown voltage element are formed in separate islands using this structure. Here, an example in which a bipolar element is formed will be described.

Island region 101°10 formed in polysilicon substrate 1
The surfaces of the side walls and bottom wall of 2 are covered with an insulating film 4, and a base 5. Impurities for emitter 6 and the like are diffused, and electrodes 9 and 10 are formed in each impurity region. Here, a high concentration impurity layer 3 is formed in the single crystal region of the island regions 101 and 102 in contact with the insulating film 4, and the high concentration impurity layer 3 is connected to the electrode 11 via the high concentration region 7 on the surface of the island region. has been done.

In the semiconductor device having the above structure, D.1. For convenience in processing the structure, the depth of each island is the same, so the depth of the island is the maximum required Break do
It is determined by the wn voltage.

<Problems to be Solved by the Invention> As described above, in a semiconductor device in which island regions have the same depth and elements are formed in these island regions, elements that can be used with low breakdown voltages have high breakdown voltages, and The depth of the island is the same as that of the island. Therefore, in the NPNTr, the saturation voltage (VCEsat) between the collector and emitter becomes high, which also causes high frequency characteristics to be significantly impaired. This is due to the on-resistance (ROM) when forming a vertical DMO3 with low breakdown voltage.
The same applies to circumstances such as an increase in The present invention has been made in view of the problems of the conventional structure described above.

Means for Solving the Problems> The present invention has the following features: 1. When forming the structure, an A semiconductor device having an I structure is formed by using semiconductor manufacturing technology with a peripheral island region having a doped bottom surface.

<Function> In the islands of high breakdown voltage elements, the required deep islands are formed, and in the islands of low breakdown voltage elements, the N-bulk layer is effectively thinned, making it possible to reduce the bulk resistance. As a result, in the case of low voltage NPNTr, the saturation voltage (VcEsat) is low and the device has excellent high frequency characteristics.
In the case of No. 3, the on-resistance (RON, ) is low and the element has excellent current characteristics, and these low-voltage elements can be formed on the same I-substrate as the high-voltage elements.

<Example> Figure 1 shows a high voltage NPNTr201 and a low voltage NPNTr2.
An example in which 02 and 1 are formed on a substrate is shown. The same parts as the conventional structure are indicated by the same reference numerals. D.

■The depth of the tank structure island is formed to match the high pressure part 201,
A high concentration N-type impurity diffusion layer 3a is selectively provided on the bottom surface of the island of the low breakdown voltage NPNTr 202 to reduce the collector resistance. The high concentration impurity diffusion layer 3a is continuous with the N+ layer 3 on the peripheral wall of the island region, and is electrically connected to the electrode 11 on the surface. With this structure, high voltage NPNTr201
In addition, it is possible to form a low breakdown voltage NPNTr 202 with excellent electrical characteristics on the same substrate.

Next, Figure 2 shows high voltage DMO3301 and low voltage DMO33.
DI 02. An example formed on a substrate is shown. In this case too,
As in the previous example, the depth of the island is formed to match the high breakdown voltage element 301, and an N-type impurity diffusion layer 3b is selectively provided at the bottom of the island of the low breakdown voltage DMO 3302, thereby achieving a structure in which substrate resistance is reduced.

The same parts as in FIG. 4 are indicated by the same reference numerals, and an impurity region for a MOS transistor (MOS transistor) in which a source and a drain 23 are formed in a base 22 is formed in the single crystal island region 2, and an impurity region is formed on the substrate. An insulating film such as a gate oxide film is formed, and a gate electrode 21, source and drain electrodes, and wiring 25 are formed.

Also in this embodiment, the selectively formed high concentration impurity diffusion layer 3b is continuous with the N type layer 3, connected to the N+ region 7 on the front side, and electrically connected to the electrode 11.

With this structure, it is possible to form a high breakdown voltage DMO 5 and a low breakdown voltage DMO 5 that can obtain a large current with low on-resistance on the same substrate.

FIGS. 3(a) to 3(e) show cross-sectional views of the manufacturing process of the semiconductor device shown in the above embodiment.

(a) Figure: An oxide film 12 is formed on the surface of the N-substrate 2, and after etching the oxide film 12 at the bottom of the island where the low breakdown voltage element is to be formed, an N-type impurity (cracks, etc.) diffusion region 3a is formed. do.

(b): In order to separate the N-substrate 2 into island shapes, the N-substrate in the portion that will become the separation region is anisotropically etched using KOH or the like.

(c) Figure: Antimony after removing the oxide film 12.

Alternatively, arsenic or the like can be diffused over the entire surface in high concentration to form an N-type layer 3 on the island peripheral wall.
will be used as a sub-collector or sub-drain in the future. After that, a thick oxide film 4 is formed.

(d) Figure: Polysilicon is grown thickly on the oxide film 4.

Figure (e): In order to separate the N-substrate into islands, the 81 substrate 2 on the side on which polysilicon 1 is not grown is polished.
A substrate with a structure in which single crystal regions are separated by an insulator is manufactured. Through the above steps, a substrate having high concentration N-type impurity diffusion regions 3a at the bottoms of the island regions is obtained, and elements are formed in each island region.

In addition to the embodiment shown here, a structure in which the combination of elements is changed, or a structure in which all elements are formed on the same substrate is also possible. Furthermore, coexistence with complementary MO3, PNPTr, etc.
It is also possible to form the substrate with different conductivity types.

In each of the above embodiments, it is desirable that the thickness of the high concentration impurity layer formed at the bottom of the island be designed in accordance with the breakdown voltage required for the element formed in the island region. In consideration of common use, it is preferable to form the same thickness on at least the other islands except for the island forming the high breakdown voltage element to prevent the process from becoming complicated.

<Effects> According to the present invention, high and low breakdown voltages can be fabricated on the same semiconductor substrate without impairing the characteristics of each element, expanding the applications of semiconductor devices and improving reliability. can.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor substrate according to an embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor substrate according to another embodiment of the present invention, and FIGS. 3(a) to (e) are sectional views of a semiconductor substrate according to another embodiment of the present invention. A cross-sectional view showing a part of the manufacturing process, and FIG. 4 is a cross-sectional view of a conventional device. 101.201.301: High voltage element, 102°20
2.302: Low breakdown voltage element, 1: Polysilicon substrate, 2:
N-substrate, 3:N+subcollector diffusion+. (N Safdrain diffusion), 4: Oxide film, 5: Base,
6: Emitter, 7: Collector, 8: Oxide film, 9: Emitter electrode, 10: Base electrode, 11: Collector electrode, 21
: Gate polysilicon, 22: Base, 23: Source,
24 Nidrein, 25 Nidrein electrode, 26 two source electrodes, 3a: High concentration diffusion at the bottom of the island. Agent Patent attorney Takeshi Sugiyama (1 other person) (a) (b) (d) (e)

Claims (1)

[Claims] 1. In a semiconductor device in which elements with different breakdown voltage characteristics are formed in a plurality of island regions electrically isolated by a dielectric isolation structure, an island region in which elements with low breakdown voltage characteristics are formed. In this case, a high concentration impurity layer is formed at the bottom of the island, which is thicker than the high concentration impurity layer formed at the bottom of the island region where the element with high breakdown voltage characteristics is formed. A semiconductor device characterized by being electrically connected to.