JPH01201943A - Method for connecting external terminal for semiconductor device - Google Patents
Method for connecting external terminal for semiconductor deviceInfo
- Publication number
- JPH01201943A JPH01201943A JP2602088A JP2602088A JPH01201943A JP H01201943 A JPH01201943 A JP H01201943A JP 2602088 A JP2602088 A JP 2602088A JP 2602088 A JP2602088 A JP 2602088A JP H01201943 A JPH01201943 A JP H01201943A
- Authority
- JP
- Japan
- Prior art keywords
- electrode frame
- internal electrode
- external terminal
- hole
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の組立て方法に関し、特に半導体装
置用外部端子と内部電極フレームこの接続方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for assembling a semiconductor device, and more particularly to a method for connecting external terminals for a semiconductor device and an internal electrode frame.
第2図は従来の接続方法で内部電極フレームと外部端子
とが接続されたフラットベース形交流制御用素子の側断
面図、第3図は一部を拡大して示す側断面図で、これら
の図において1はベース板で、このベース板1は半導体
素子2が発する熱を外部に放熱しやすくするために金属
等の熱伝導性の良い材料によって形成されている。3は
絶縁部材としてのセラミック基板で、このセラミック基
板3には前記ベース板1、半導体素子2および後述する
端子とが固着する電極3a、3b、3cが形成されてい
る。4は前記セラミック基板3の電極3bと前記半導体
素子2とを接続するための導電板である。すなわちベー
ス板1の半導体素子取付部1a上にセラミック基板3の
裏面に形成された電極3aを固着させ、このセラミック
基板3の上面に形成された電極3bに導電板4を固着さ
せ、さらに、その上に半導体素子2を固着させることに
よって、半導体素子2が導電板4とセラミック基板3を
介してベース板1上に固着されることになる。5は前記
半導体素子2の電極(図示せず)と前記セラミック基板
3の電極3cとを接続するための内部電極フレーム、6
.7は外部装置(図示せず)と半導体素子2とを接続す
るだめの端子で、これら端子6,7は、その一部分が枠
体8の保持部8aに埋設されることによって枠体8と一
体的に形成され、これら端子6,7の下端部6a 、7
aは前記電極3b 、3cにクリーム半田9によって固
着されている。10は前記枠体8内に満たされることに
よって半導体素子2.電極3b〜3c+導電板4゜内部
電極フレーム5等を封止するための不透過性樹脂からな
る封止樹脂である。Figure 2 is a side sectional view of a flat base type AC control element in which the internal electrode frame and external terminals are connected using the conventional connection method, and Figure 3 is a partially enlarged side sectional view. In the figure, reference numeral 1 denotes a base plate, and this base plate 1 is made of a material with good thermal conductivity, such as metal, in order to easily dissipate the heat generated by the semiconductor element 2 to the outside. Reference numeral 3 designates a ceramic substrate as an insulating member, and electrodes 3a, 3b, and 3c are formed on this ceramic substrate 3 to which the base plate 1, semiconductor element 2, and terminals to be described later are fixed. Reference numeral 4 designates a conductive plate for connecting the electrode 3b of the ceramic substrate 3 and the semiconductor element 2. That is, the electrode 3a formed on the back surface of the ceramic substrate 3 is fixed on the semiconductor element mounting portion 1a of the base plate 1, the conductive plate 4 is fixed on the electrode 3b formed on the upper surface of this ceramic substrate 3, and then the By fixing the semiconductor element 2 thereon, the semiconductor element 2 is fixed onto the base plate 1 via the conductive plate 4 and the ceramic substrate 3. 5 is an internal electrode frame for connecting the electrode (not shown) of the semiconductor element 2 and the electrode 3c of the ceramic substrate 3; 6;
.. 7 is a terminal for connecting an external device (not shown) and the semiconductor element 2, and these terminals 6 and 7 are integrated with the frame 8 by being partially embedded in the holding part 8a of the frame 8. The lower ends 6a, 7 of these terminals 6, 7
A is fixed to the electrodes 3b and 3c with cream solder 9. 10 is filled in the frame 8 to form a semiconductor element 2. Electrodes 3b to 3c + conductive plate 4° This is a sealing resin made of an impermeable resin for sealing the internal electrode frame 5 and the like.
このように構成されたフラットベース形交流制御用素子
を組立てるには、先ず、ベース板1上にセラミック基板
3および導電板4を介して半導体素子2を固着させる。In order to assemble the flat base AC control element constructed in this manner, first, the semiconductor element 2 is fixed onto the base plate 1 via the ceramic substrate 3 and the conductive plate 4.
次で、内部電極フレーム5によって半導体素子2の電極
(図示せず)とセラミック基板3の電極3cとを接続す
る。そして、この電極3cに端子7をクリーム半田9に
よって同温させると共に、電極3bに端子6を同じくク
リーム半田9によって固着させる。しかる後、枠体8内
に封止樹脂10を注入することによって組立てが終了す
る。すなわち、内部電極フレーム5と端子7は、第3図
に示すようにそれぞれセラミック基板3上の電極3C上
に半田付けされることによって接続されることになυ、
半導体素子2の電極と端子7が接続されることになる。Next, the electrodes (not shown) of the semiconductor element 2 and the electrodes 3c of the ceramic substrate 3 are connected using the internal electrode frame 5. Then, the terminal 7 is heated to the same temperature as the electrode 3c using the cream solder 9, and the terminal 6 is also fixed to the electrode 3b using the cream solder 9. Thereafter, the sealing resin 10 is injected into the frame 8 to complete the assembly. That is, the internal electrode frame 5 and the terminal 7 are connected by being soldered onto the electrode 3C on the ceramic substrate 3, respectively, as shown in FIG.
The electrodes of the semiconductor element 2 and the terminals 7 will be connected.
しかるに、このような内部電極フレーム5と端子7この
接続方法によって組立てられた半導体装置においては、
第3図に示すように、電極3C上に内部電極フレーム5
および端子7が載置された状態で半田付けされているた
め、半田付は不良を起こしやすい。半田付は不良が発生
した場合には特性不良(オープン不良)を起こすので、
このような接続方法によって内部電極フレーム5と端子
7とが接続された半導体装置は信頼性が低かった。However, in a semiconductor device assembled by this connection method between the internal electrode frame 5 and the terminal 7,
As shown in FIG. 3, an internal electrode frame 5 is placed on the electrode 3C.
Since the terminal 7 is soldered while being mounted, soldering is likely to cause defects. If a soldering defect occurs, it will cause a characteristic defect (open defect).
A semiconductor device in which the internal electrode frame 5 and the terminal 7 were connected by such a connection method had low reliability.
本発明に係る半導体装置用外部端子の接続方法は、予め
内部電極フレームの外部端子側端部に透孔を穿設すると
共に、この透孔の上方を覆う延在部を前記外部端子に設
け、内部電極フレームを前記基板の電極に半田付けした
後、前記延在部で内部電極フレームを押圧させて外部端
子を半田付けするものである。A method for connecting an external terminal for a semiconductor device according to the present invention includes: drilling a through hole in advance at the end of the internal electrode frame on the external terminal side, and providing the external terminal with an extending portion that covers the upper side of the through hole. After the internal electrode frame is soldered to the electrodes of the substrate, the internal electrode frame is pressed by the extended portion to solder the external terminal.
延在部で内部電極フレームを押圧させて外部端子を半田
付けすると、内部電極フレームの透孔内および外部端子
の延在部と内部電極フレームこの間に半田が充填される
ことになシ、透孔内で凝固した半田によって内部電極フ
レームが強固に半田付けされる。When the external terminal is soldered by pressing the internal electrode frame with the extension part, solder will be filled in the through hole of the internal electrode frame and between the extension part of the external terminal and the internal electrode frame. The internal electrode frame is firmly soldered by the solder solidified inside.
以下、その構成等を図に示す実施例によ勺詳細に説明す
る。Hereinafter, the structure and the like will be explained in detail with reference to the embodiment shown in the drawings.
第1図は本発明に係る接続方法によって内部電極フレー
ムと端子とが接続された状態を要部を拡大して示す側断
面図で、同図において前記従来例で説明したものと同一
もしくは同等部材については同一符号を付し、ここにお
いて詳細な説明は省略する。同図において、11は透孔
で、この透孔11は、内部電極フレーム5の端子7側端
部に内部電極フレーム5の成形時に同時に穿設すること
によって形成されている。12は前記内部電極フレーム
5を上方から押圧するための抑圧片で、この押圧片12
は端子7のそれぞれの下端部7&を延在させて設けられ
、前記内部電極フレーム5の透孔11の上方を覆う長さ
寸法および幅寸法をもって形成されている。FIG. 1 is an enlarged side sectional view showing the main parts of a state in which an internal electrode frame and a terminal are connected by the connection method according to the present invention. The same reference numerals are given to the same reference numerals, and detailed explanation thereof will be omitted here. In the figure, reference numeral 11 denotes a through hole, and the through hole 11 is formed at the end of the internal electrode frame 5 on the terminal 7 side at the same time as the internal electrode frame 5 is molded. 12 is a pressing piece for pressing the internal electrode frame 5 from above; this pressing piece 12
are provided by extending the lower end portions 7& of the terminals 7, and are formed to have a length and a width that cover the upper portions of the through holes 11 of the internal electrode frame 5.
このように透孔21が穿設された内部電極フレーム5と
抑圧片12を有する端子Iとを接続するには、先ず、セ
ラミック基板3の電極3cに、−端が半導体素子(図示
せず)の電極に接続された内部電極フレーム5をクリー
ム半田9を介して接続させる。次で、この内部電極フレ
ーム5の透孔11側端部を押圧片12で押圧させて端子
7をクリーム半田9を介して前記電極3cに接続させる
。In order to connect the internal electrode frame 5 in which the through hole 21 is formed in this manner and the terminal I having the suppressing piece 12, first, a semiconductor element (not shown) is connected to the electrode 3c of the ceramic substrate 3 at the negative end. The internal electrode frame 5 connected to the electrode is connected via cream solder 9. Next, the end portion of the internal electrode frame 5 on the side of the through hole 11 is pressed by the pressing piece 12 to connect the terminal 7 to the electrode 3c via the cream solder 9.
すなわち、抑圧片12で内部電極フレーム5を押圧する
ことにより透孔11内および内部電極フレーム5と抑圧
片12この間にクリーム半田9が充填されることになシ
、内部電極フレーム5と端子7とがそれぞれ半田付けさ
れることになる。That is, by pressing the internal electrode frame 5 with the suppressing piece 12, the cream solder 9 is filled in the through hole 11 and between the internal electrode frame 5 and the suppressing piece 12, and the internal electrode frame 5 and the terminal 7 are will be soldered to each other.
したがって、透孔11内で凝固したクリーム半田9によ
って内部電極フレーム5が強固に半田付けされることに
なる。Therefore, the internal electrode frame 5 is firmly soldered by the cream solder 9 solidified within the through hole 11.
なお、本実施例ではフラットベース形交流制御用素子に
ついて説明したが、本発明はこのような限定にとられれ
ること々く、例えばパワートランジスタ等であっても同
等の効果が得られる。In this embodiment, a flat base AC control element has been described, but the present invention is not limited to this, and the same effect can be obtained even with a power transistor or the like.
以上説明したように本発明によれば、予め内部電極フレ
ームの外部端子側端部に透孔を穿設すると共に、この透
孔の上方を覆う延在部を外部端子に設け、内部電極フレ
ームを前記基板の電極に半田付けした後、前記延在部で
内部電極フレームを押圧させて外部端子を半田付けする
ため、延在部が内部電極フレームを押圧することにより
内部電極フレームの透孔内および延在部と内部電極フレ
ームこの間に半田が充填されることになり、透孔内で凝
固した半田によって内部電極フレームが強固に半田付け
されることになる。したがって、半田付は不良を起こし
にくく、信頼性の高い高品質な半導体装置を得ることが
できる。As explained above, according to the present invention, a through hole is previously formed at the end of the internal electrode frame on the external terminal side, and an extending portion covering the upper part of the through hole is provided on the external terminal, and the internal electrode frame is After soldering to the electrodes of the board, the extension part presses the internal electrode frame to solder the external terminal. Solder is filled between the extension portion and the internal electrode frame, and the internal electrode frame is firmly soldered by the solder solidified within the through hole. Therefore, soldering is less likely to cause defects, and a highly reliable and high quality semiconductor device can be obtained.
第1図は本発明に係る接続方法によって内部電極フレー
ムと外部端子とが接続された状態を要部を拡大して示す
側断面図、第2図は従来の接続方法で内部電極フレーム
と外部端子とが接続されたフラットベース形交流制御用
素子の側断面図、第3図は一部を拡大して示す側断面図
である。
3・拳・・セラミック基板、3C@φ・Φ電極、5・・
・・内部電極フレーム、7・・・・端子、9・・・・ク
リーム半田、11・・・・透孔、12・・・・押圧片。FIG. 1 is an enlarged side cross-sectional view showing the main parts of a state in which an internal electrode frame and an external terminal are connected by the connection method according to the present invention, and FIG. 2 is a side sectional view showing an internal electrode frame and an external terminal connected by a conventional connection method. FIG. 3 is a partially enlarged side sectional view of a flat base type AC control element connected to the AC control element. 3. Fist...ceramic substrate, 3C@φ/Φ electrode, 5...
...Internal electrode frame, 7...Terminal, 9...Cream solder, 11...Through hole, 12...Press piece.
Claims (1)
部端子とを基板の同一電極に半田付けし両者を接続させ
る半導体装置用外部端子の接続方法において、予め内部
電極フレームの外部端子側端部に透孔を穿設すると共に
、この透孔の上方を覆う延在部を前記外部端子に設け、
内部電極フレームを前記基板の電極に半田付けした後、
前記延在部で内部電極フレームを押圧させて外部端子を
半田付けすることを特徴とする半導体装置用外部端子の
接続方法。In a method for connecting an external terminal for a semiconductor device in which an internal electrode frame and an external terminal, one end of which is connected to a semiconductor element, are soldered to the same electrode on a substrate to connect the two, the external terminal side end of the internal electrode frame is drilling a hole and providing the external terminal with an extension portion that covers the upper part of the through hole;
After soldering the internal electrode frame to the electrodes of the board,
A method for connecting an external terminal for a semiconductor device, characterized in that the external terminal is soldered by pressing the internal electrode frame with the extension part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2602088A JPH01201943A (en) | 1988-02-05 | 1988-02-05 | Method for connecting external terminal for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2602088A JPH01201943A (en) | 1988-02-05 | 1988-02-05 | Method for connecting external terminal for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01201943A true JPH01201943A (en) | 1989-08-14 |
Family
ID=12182014
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2602088A Pending JPH01201943A (en) | 1988-02-05 | 1988-02-05 | Method for connecting external terminal for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01201943A (en) |
-
1988
- 1988-02-05 JP JP2602088A patent/JPH01201943A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| IT1280673B1 (en) | MODULE OF HIGH POWER SEMICONDUCTOR DEVICES WITH LOW THERMAL RESISTANCE AND SIMPLIFIED MANUFACTURING METHOD | |
| JP2717076B2 (en) | Surface mount microminiature current fuse | |
| JPH1082698A (en) | Temperature sensor having resistance bulb | |
| JP4301096B2 (en) | Semiconductor device | |
| JPH01201943A (en) | Method for connecting external terminal for semiconductor device | |
| JPH05315467A (en) | Hybrid integrated circuit device | |
| JPH0635382Y2 (en) | Lead terminal mounting structure for hybrid integrated circuit | |
| JPS6134632Y2 (en) | ||
| JP2770664B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH01106452A (en) | Semiconductor device | |
| JPH0249727Y2 (en) | ||
| JPS63208250A (en) | Package structure of integrated circuit | |
| JP2024179082A5 (en) | ||
| JPH0864980A (en) | Semiconductor device and manufacturing method thereof | |
| JPH11218443A (en) | Pyroelectric sensor | |
| JP2665198B2 (en) | Power amplifier transistor mounting structure | |
| JPS6011651Y2 (en) | semiconductor equipment | |
| JPS5852641Y2 (en) | Positive characteristic thermistor | |
| JPS5813570Y2 (en) | temperature relay | |
| JP3487355B2 (en) | Piezoelectric oscillator | |
| JPS607488Y2 (en) | semiconductor equipment | |
| JPH0349398Y2 (en) | ||
| JPH0732230B2 (en) | Semiconductor device | |
| JPH01281759A (en) | Semiconductor device | |
| JPS6130748B2 (en) |